Henry Ding Email & Phone Number

San Jose, Ca, Us

Alhambra, Ca, Us

My role covers DSP, ARM processors and FPGA, SoC FPGA design, verification, validation and lab bring up.

San Jose, Ca, Us

During 12 years at Cisco, I have continuously contributed to the successful released new products by participating the timely and quality delivery of aggressive and challenging full life-cycle development FPGA projects. As a design verification engineer, I worked with design engineers closely, wrote test plans, created test cases against functional specs, implemented reference models and test environments, debugged test failures and located RTL logic bugs, provided coverage reports and reviewed with design engineers. As a FPGA design engineer, I implemented and delivered FPGA/CPLD design individually, starting from the scratch, including writing functional spec according to the requirements, pin assignments, RTL coding, synthesizing, closing time, simulating, bringing-up in the lab, testing with board engineers, diagnostic engineers and sw engineers, and lab debugging. Languages: Verilog, System Verilog, VHDL, Unix Shell ScriptsVendors been working with: Xilinx, Lattice, IntelTools: VCS, Modelsim, Git, Clearcase, cvsTrainings: • Synopsys System Verilog training courses• Synopsys UVM training courses• Xilinx FPGA design training courses• Altera FPGA design training courses

Master Of Science, Ms, Electrical Engineering (Dsp)

Bachelor Of Science, Bs, Electrical Engineering (Electromagnetic Field And Microwave Technology)