Henry Hoang Email & Phone Number

• Managed business unit (BU) operations, platform development budget and expenses, ODM project developments, customer programs and issue resolutions. Led $10M system hardware development budget for organization of 250+.
• Oversaw key customer programs, conducting weekly review of internal and customer accounts with BU marketing, engineering, and customer support leadership team.
• Managed platform development budget and expenses, ODM SOW / contract, customer and engineering order allocation, delivering systems and SOCs on-time.
• Reduced platform development expenses $3M compared to previous generation by minimizing cross-functional system requirements and per system cost.
• Designed CRB systems, platform reference design collaterals, enabling customer's evaluation, design of ARM server, leveraging ODM, IBV partners, achieving cost-effective solutions

Santa Clara, California, US

• Directed globally located engineering team of 30+ hardware, software and systems engineers to design reference systems, platform design collaterals, and embedded software solutions as part of customer enablement and.
• Supervised overseas engineers to design reference systems, including firmware and BIOS solutions via IBV partners and managed ODM NPI operations, delivering CRB systems to team and customers on schedule.
• Spearheaded system architecture proposal, and review of customer designs, producing low-cost CRB systems, reference designs and design collaterals, enabling OEM / ODM customers in shortening product design cycle and.

• Oversaw engineering team of 15+ talented hardware, systems engineers in start-up environment to design SOC validation boards, reference systems, and design collaterals for ARM Server CPU market. Managed engineering.
• Supervised engineering team, designing high-quality validation boards for SOC bring-up / validation, characterization and software development, managing NPI operations via contract manufacturer (CM).
• Provided POC systems, reference design collaterals, facilitating ODM / OEM customer designs through system architecture proposal, design review.
• Re-built systems engineering team with critical talent required for high-speed fabric-based SoC development, delivering high-quality validation boards on schedule.

Houston, Texas, US

• Drove architect, design of high performance, modular, and stackable network security equipment.
• Integrated TippingPoint hardware engineering development, release, sustaining process into global engineering environment, ensuring products met quality and support standards.
• Fostered collaborative teamwork with HP global organizations, leveraging existing resources to save cost.

• Led hardware engineering department of 25+ engineers responsible for system hardware / FPGA design, validation, release and supported intrusion prevention network security systems. Managed engineering labs, R&D CapEx.
• Provided organizational leadership and direction, supervising generation and control of technical processes and documentation, building, coaching, and mentoring teams.
• Managed architect, development of complex, embedded FPGA hardware acceleration network security products delivering 10x performance of competitor software-based systems.
• Designed multiple generations of network security products for 1GE, 10GE, 40GE markets with incremental system performance and lower cost.

San Jose, CA, US

• Managed hardware engineering team of 12+ engineers to design Ethernet switch ASICs, systems for Catalyst product family.
• Designed multiple generation of Ethernet Switches for Cisco Catalyst 3750 Series, 3560 Series using DSBU Switch ASICs and off-the-shelf NPU.
• Managed hardware engineering team to design, validate, release custom ASICs, system platforms for several large-scale programs, within multimillion-dollar budget.
• Participated in strategic resources planning, coaching and mentoring talent in organization. Technical Leader, May 1998 - Mar 2001
• Lead architect of the NI-4 and 8x DSL Linecards developments for 6100 DSLAM products. Developed 626, 627 ATM25 to ADSL modem using FPGA for cell buffer queuing and scheduling.
• Member of the SuprSAR ASIC development team, responsible for interface logic to embedded CPU. Coded & simulated design, including gate level simulation using VCS and Synopsys Verilog compiler.

• Developed a DS1 IMA interface module using FPGA and DS1 framer for Ethernet to ATM router

Singapore, SG

• Developed a cell-based, DMT ADSL modem using ADI chipset, proprietary ASIC, and IDT RISC processor.

• Co-Architecturer, inventor of the CellRunner Switching Technology. Awarded three U.S. patents.
• Developed wire speed 6-port Fast Ethernet switch using RISC processors and FPGA devices.
• Developed 45K gates ASIC and 12-port Fast Ethernet switch system.
• Managed the cross functional product development team to participate in product concept review, project plan, hardware, firmware design review.

• Developed industry first tri-segment Ethernet stackable and Snappable hub with ERA Architecture.

US

• Developed a MAC address lookup daughter board to provide wire-speed FDDI to Ethernet bridging. Integrated the complete board into an ASIC. Developed driver for the ASIC.

• Developed and maintained hardware diagnostics and test fixtures for process control systems