My interest lies in all aspects of digital ASIC design, but what truly excites me is executing a complex design and tweaking it to satisfy the constraints of timing, power, and area.At Cadence, I have been instrumental in advancing CPU design by contributing to the development of a RISC-V processor platform trace module. This role utilizes my expertise in ASIC frontend design and complements my Master's studies in Computer Engineering at NC State University. In collaboration, we are bridging the gap between state-of-the-art technological advancements and academic research, especially in the fields of Computer Architecture and Digital Design.Previously at Infineon Technologies, we achieved a 12% reduction in design time by innovating SOC design methodologies, showcasing my knack for enhancing efficiency and leading a team to automate complex tasks. Now, I'm focused on translating these competencies into my current role, committed to advancing the industry with each breakthrough.