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Prateek Chandra is listed as Actively looking for full-time opportunities starting June 2025 | Ex Cadence - CPU RTL Design Intern | MS in Computer Engineering at NC State University 2023-25 | Ex Infineon | BIT Mesra based in Raleigh, North Carolina, United States. AeroLeads shows a matched LinkedIn profile for Prateek Chandra.
Prateek Chandra previously worked as CPU RTL Design Engineering Intern at Cadence Design Systems and Staff Engineer - Silicon Design Methodology at Infineon Technologies. Prateek Chandra holds Master Of Science - Ms, Computer Engineering from North Carolina State University.
My interest lies in all aspects of digital ASIC design, but what truly excites me is executing a complex design and tweaking it to satisfy the constraints of timing, power, and area.At Cadence, I have been instrumental in advancing CPU design by contributing to the development of a RISC-V processor platform trace module. This role utilizes my expertise in ASIC frontend design and complements my Master's studies in Computer Engineering at NC State University. In collaboration, we are bridging the gap between state-of-the-art technological advancements and academic research, especially in the fields of Computer Architecture and Digital Design.Previously at Infineon Technologies, we achieved a 12% reduction in design time by innovating SOC design methodologies, showcasing my knack for enhancing efficiency and leading a team to automate complex tasks. Now, I'm focused on translating these competencies into my current role, committed to advancing the industry with each breakthrough.
A career timeline built from the work history available for this profile.
Austin, Texas, United States
● Engineered RTL design for a cutting-edge program flow tracing hardware on a RISC-V CPU, generating real-time messages for every program flow change in compliance with the RISC-V N-Trace standard.● Developed an innovative compression algorithm (as a stretch goal) that optimized internal storage (FIFO) width, effectively handling varying rates of message generation and propagation.
Bengaluru, Karnataka, India
● Conceptualized a methodology to enable platform based heirarchical instantiation and interconnect RTL generation for automotive body control SOCs; helped reduce design time by 12%.● Ideated an innovative methodology to use systems engineering concepts (Model Based System Engineering) to enable heirarchical structure and interconnect using abstract models of IPs (defined in Enterprise Architect) of an SoC; led a team of three members in the process.● Conducted 50+ technical interviews for hiring EDA/Design Methodolgy engineering professionals for the team.● Took the initiative to function as a key interface between the team and stakeholders to enable smooth execution, delivery and maintenance of projects.
Bangalore
● Enhanced a methodology to create IP level UPF with insertion of isolation and retention cells from abstract specification of supply sets, power domains and power distribution strategies; helped improve inter-IP supply set naming consistency and accelerate integration at top-level by 17%.● Streamlined a methodology to assimilate SoC Firmware Configuration Data for different products in the family improving the existing process duration to 60 minutes from 1 week.● Conceptualised and implemented a novel technique to maintain backwards traceability with SoC 's requirements and design implementation to eliminate late error detection thereby resulting in recurring savings of 7.8k euros annually.
Bengaluru, Karnataka, India
● Built a prototype from scratch a cool smart home device - Smart Plug majorly using Infineon Technologies' products.● This device allowed users to access their home sockets through a mobile/laptop connected to the network same as the Smart Plug
Relevant Coursework: ECE 563: Microprocessor Architecture ECE 506: Architecture of Parallel Computers ECE 564: ASIC and FPGA Design.
Relevant Coursework: Microprocessor and Microcontroller - 8086 Digital Electronics Fundamentals of C, Data Structures and Algorithms.
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Prateek Chandra is listed as Actively looking for full-time opportunities starting June 2025 | Ex Cadence - CPU RTL Design Intern | MS in Computer Engineering at NC State University 2023-25 | Ex Infineon | BIT Mesra.
Prateek Chandra is based in Raleigh, North Carolina, United States.
Prateek Chandra has worked for Cadence Design Systems and Infineon Technologies.
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Prateek Chandra holds Master Of Science - Ms, Computer Engineering from North Carolina State University.
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