Hitesh Katariya Email & Phone Number

VLSI DOMAIN SKILLS--------------------------- • Digital Electronics • HDL: Verilog • HVL: System Verilog • TB Methodology: UVM • Protocols: APB, UART, I2C, SPI • EDA Tools: Modelsim, Quartus Prime, Questasim.VLSI RTL SKILLS---------------------- • Digital Skills : Combinational and Sequential circuits • FSM • Memories• Verilog : Data types • Operators • BA and NBA • Delays in Verilog • Begin-end and fork-join Blocks• System tasks and Function • Compiler directive • FSM Coding.VLSI VERIFICATION SKILLS------------------------------------ • System Verilog HVL: Data Types • Memories • Interface • OOPS • Constraint Randomization • Threads • Functional coverage • CRCDV • SV Testbench (Hands on SV Testbench)• Universal Verification Methodology: UVM Objects and Components • UVM Factory • UVM Phases •UVM Configuration • TLM • Virtual Sequence and Sequencer • UVM Testbench (Hands on UVM Testbench).PROJECTS--------------1) FPGA project on Zyboz7 board using Verilog and tool vivado2) AMBA APB Protocol: Designed using Verilog HDL and tested by UVM test bench.3) Synchronous FIFO-RTL Design and Verification: Implemented the RTL design of synchronous FIFO in Verilog and tested by System Verilog test bench and UVM test bench. Please feel free to contact me for further information.hiteshk14095@gmail.com || +91 9724234633Thank you for reading my career summary.

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  Government Engineering College (Gec) Bhavnagar

  Electronics And Communications Engineering