- learn fundamentals of High-level Synthesis targeting for Xilinx Vitis HLS Tool, including: data types,optimization directives, loop optimization, pipelining- do a final project about synthesizing to RTL a hardware module to calculate monthly balance, using C/C++ language and Vitis HLS Tool

Learn the necessary theory for designing large-scale integrated circuits, targeting specifically for digital IC.Get familiar with the overall flow of digital design; and the main roles contributing to designing of a chip, such as RTL Engineer, Verification Engineer, Physical Design Engineer.