ASIC Logic Design

In a collaborative effort, co-design and micro-architect of IP bridge (SCA) connecting the CHI (Coherent Hub Interface) of an ARM processor cluster (A72/A53) with NXP's coherent interconnect CoreNet interface.Worked closely with main architect, and verification lead.Duties include supporting unit verification effort with processor VIP, as well as supporting the sub-system verification effort with an ARM core connected to the CHI to CoreNet Interconnect IP bridge (SCA).Led debug effort of high priority (post silicon) customer issues with mature Ethernet IPs from several SoC products. Employed new formal verification Cadence tool, Jasper, to track down root cause of one defect.

In a collaborative effort, co-designed and micro-architected accelerator IP (Statistic Engine, STE) for a Network Processor of the LS2 SoC series of Freescale products. Design included AXI-3 AMBA interfaces and a cache-like buffer.Achieved quick turn around in bug resolution from external vendor by filtering and identifying real RTL coding and clock domain crossing issues, maintaining a trusted relationship.For a PHY Wrapper sub-system IP, used Mentor graphics 0in/Questa to identify and resolve CDC (clock domain crossing) issues of several sub-blocks. Salvaged key Giga-bit Ethernet Controller IP (with TCP offloading features) inherited from former employees by participating in SWAT team to make logic fix or identify work-arounds for late IP defects. - IP contained both functional and clock domain crossing (CDC) issues.- Owned TX path logic, fixes, improvements, and enhancements. Identified and implemented metal fixes. - Used in 10s of key SoC products (MPC8548, MPC8578...), including division's best selling SoCImproved performance of Giga-bit TX Ethernet path from maximum of 700Mbps to achieve line rate of 1Gbps.Micro-architected and designed PCS (Physical Coding Sub-link) located between vendor MAC(s) and SerDes hard-IP for: - HyperTransport, - PCI Express Gen1, - SRIO (Serial Rapid IO) Defined digital verification test method for variation in bit streams received from SerDes to address hold in verification coverage.Micro-architected and designed Ethernet Controller's DMA sub-block. Issued disclosure for 4 patents.

Using Perl, verified adherence to internal interconnect bus rules for the V-Comp (Vector Computation) chip, a graphics processor.Co-inventor of method used to test internal peripheral bus characterized by a variable sequence of bus activity. Monitored internal bus with cycle accuracy.Modified IP designs for reuse in companies' first SoC (PowerPC based). Later reused in additional SoC products (MPC8240, MPC8245, MPC107):- EPIC- I2C- DUART

Owned the development of the test plan and the execution of the plan for new adapter boards (including firmware) and chip designs to verify claimed (specification) functionality.Wrote Fortran and C programs used in testing DUTs. (Devices Under Test).