Byron Ho Email & Phone Number

San Diego, California, United States

• Leading large, cross-functional engineering teams to develop and implement new front-end-of-line process inventions for Intel 10/7/4 nodes
• Well-versed in device physics and analyzing electrical data to identify improved processes and layout interactions
• Proficient in model-based problem solving, synthesizing and mining yield, electrical, defect, and FA data to set up DOEs that rapidly zero in on root causes and solutions
• Excel at project management by balancing deadlines, resources, and mental well-being of the team
• Demonstrated track-record of achieving improved yield, performance, and reliability

Portland, Oregon Area

• Managed Intel 4 design rule definition and ensured on-time DR delivery for PDK schedule
• Collaborated between design (standard library, collateral, memory) and fab teams to implement new rules that improved PPA/design ease-of-use and yield/DFM

Berkeley, CA

• Comprehensive TCAD simulation and fabrication of deep submicron (Lg ~ 10nm) Si and SiGe channel devices in various device architectures to quantify their benefits toward continued scaling

Hopewell Junction, NY

• Electrical characterization and design of 22nm SOI CMOS platform. Investigated impact of fabrication process on high-k/metal gate workfunction and channel mobility.

Doctor Of Philosophy (Ph.D.), Electrical And Electronics Engineering

"Evolutionary MOSFET Structure and Channel Design for Nanoscale CMOS Technology"

Master Of Science (M.S.), Electrical And Electronics Engineering

Bachelor Of Science (B.S.), Electrical Engineering

Activities and Societies: Eta Kappa NuSumma Cum Laude