Howard David Email & Phone Number

Portland, Oregon, United States

Pacific Northwest And Global

Technology, research and development consultant with extensive experience in memory subsystem architecture and product design. Experienced with servers, clients and SOC devices, for all phases of product life cycle including research, pathfinding, product opportunity, architectural specification, design and validation. Available for JEDEC representation, and for expert witness testimony.

Portland, Oregon Area

Architecting innovative memory solutions for future SoC designs. Authored High-level Architecture Specification for a high-performance DRAM Memory Controller. Developed SoC future product roadmaps for enabling DDR5, LP-DDR5, GDDR6 and HBM3 DRAM technologies.

Portland, Oregon Area

Memory subsystem expert guiding the development of custom processor silicon for Huawei IT andinfrastructure products. Representing Huawei at the JEDEC standards body: JC-40, JC-42 and JC-45committees and task groups. Innovatively impacting the DDR5 DRAM, logic and DIMM specifications.

Product Engineering Group

Silicon architect for two generations of Embedded DRAM which enabled record breaking integrated graphics performance in the Intel Iris Pro Graphics 5200 and 6200 products, with the 2nd generation eDRAM parts going into production on first silicon, and incorporated as an IP block into many future products.Beginning with research at Intel Labs, drove Intel toward improved memory subsystem power management, including dynamic voltage and frequency scaling (DVFS) of memory controllers and DRAM. Defined memory power management architecture specifications for tablet/phone SOC products.Pioneered Running Average Power Limit (RAPL) for memory, with patents and publications at Intel Labs, with product intercepts for server and SOC, and architected RAPL electrical throttling for SOC memory subsystem to dramatically reduce the Bill of Material (BOM) cost of power delivery.Transformed power measurement in platform validation, by championing one-time calibration of voltage regulator and power supply telemetry, eliminating the requirement for expensive processor interposers and custom power measurement versions of validation boards.

Intel Labs

Primary researcher for off-die memory, for Intel’s DARPA sponsored Ubiquitous High Performance Computing (UHPC) project, identifying technological innovations to achieve 5x reduction in energy per bit for on-package 3D stacked memory, leading directly to $19M award from DOE for “Fast Forward R&D -- Processor and Memory.”Enabled major server and client product innovations by architecting and leading the team that developed a DIMM tracer for capturing unlimited DIMM command and address traces, used for all architectural studies requiring long traces including two level memory and row hammer investigations.

Digital Enterprise Group, Memory Pathfinding

Led Intel “Physical KIT team” delivering board layout, signal integrity, thermal solution, and power delivery for Fully Buffered DIMM (FB-DIMM) giving Intel competitive advantage in memory capacity and bandwidth for its server products, dramatically accelerating its server market share. Leadership role recognized with Intel’s highest corporate-level technical award, the Intel Achievement Award.Representing Intel at JEDEC standards organization, drove DDR, DDR2, DDR3, R-DIMM and FB-DIMM specifications to meet requirements for Intel products, including new features and specifications such as tQH, tFAW, Idd7, Output Slew Rate, BL4 Chop and reversible SPD write protect. Introduced new DDR, DDR2 and FB-DIMM memory technologies with presentations at Intel Developer Forum. Honored with JEDEC’s most significant award for technical achievement, the JEDEC Technical Recognition Award.

Enterprise Product Group, Technical Marketing

Developed technical marketing collaterals and worked closely with “big-iron” server OEMs so they met Intel’s “Launch + 1Q” schedule objective for delivery of 8-way to 64-way platforms featuring Intel Deschutes Slot 2 processors.

Server Business Unit

Architected and implemented the Xpress architecture, which put Intel on the map for 2-way and 4-way servers, in the top 2 of x86 server system suppliers. Over a 4 year run, the Xpress asynchronous modular architecture supported all of the i486 and Pentium processors with just two baseboards. Took initiative to start randomized stimulus for pre-Si system simulations, which was very effective catching logical errata, and pioneered multi-client stress post-Si testing, which evolved to become Intel’s Server Validation Lab.

Master Of Science (M.S.), Electrical Engineering

Bachelor Of Science (B.S.), Physics

Activities and Societies: Programmer at MSU Cyclotron Laboratory

Education record