Customer support Lead training Migrate legacy designs Develop custom flows, utilities Develop HSPICE, CDL and Verilog netlisters Discuss new features with customers, define and provide requirements for R&DNew features prototyping on TclReviewing product specifications.Managing a team of Corporate Application Engineers working on the Synopsys' Custom Design products

Coordinate 5 person team worksDuring 2007 also performed responsibilities QA department managerGive tasks to team members and check the quality of their workWork with customers: provide custom solutions, develop design flowPrepare training materials and demo designs for customersTestcases development/reviewSend reports to high level managers

Conducted lectures and practical courses for BS and MS students in department of Applied MathematicsDigital CircuitsIntroduction to VLSI DesignBasic electronics circuitsVerilog HDL

Started as engineer responsible for development and verification of specific DSP functions: CRC, Scrambler, Error Correction Code (Reed-Solomon encoder/decoder) on Altera FPGA family using Verilog HDL.During the 2 last years coordinating a 6-person team in complex projects, responsible for design, prototype, and test bench, layout and debug mixed-signal IC. Development of PCBs for testing hardware prototypes elaborated by the team. Providing training courses on Verilog HDL for the company employees.Key Projects:Functional and timing verification of CPLD design developed by HW group for Legerity Corporation.PCI2HPI. Design bridge on Altera PLD between MPC8280 PCI bus and 8 bit HPI ports of several TMS320VC5502 DSPs (at least 4).Created guideline with recommendations for HDL coding and prototyping the core of FPGA for the company's internal usageConcentrator. Create interface on Altera and Xilinx FPGAs between E1/T1 channels and HPI port of TMS320CV5510 DSP using Quartus and ISE packages.Test board design for USB - via - RF interconnection. Writing Verilog code for Altera EPF10K10ATC144-1 FPGA, that should be used for configuration of "Intersil" base band processor, RF and IF parts, and also for the control of USB traffic.Design controller implemented in Altera EPF10K10ATC144-3 FPGA and support software package for programming Maxim DS2174 EBERT through RS232 interface.Sigma-Delta ADC: Design an IIR decimation filter. Design simulations were done using Mentor Modelsim and Tanner T-Spice simulators. P&R was made using Tanner L-Edit layout editor for HP 0.5um Fabrication process.