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Daniel Hsu Email & Phone Number

Sr Manager, DFT at Ambarella Inc
Location: Santa Clara, California, United States 9 work roles 3 schools
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Role
Sr Manager, DFT
Location
Santa Clara, California, United States

Who is Daniel Hsu? Overview

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Quick answer

Daniel Hsu is listed as Sr Manager, DFT at Ambarella Inc, based in Santa Clara, California, United States. AeroLeads shows a matched LinkedIn profile for Daniel Hsu.

Daniel Hsu previously worked as Sr Staff DFT Engineer at Ambarella Inc and Staff DFT & Design Engineer at Ambarella Inc. Daniel Hsu holds Master'S Degree, Electronics Engineering from National Chiao Tung University.

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Email format at Ambarella Inc

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Ambarella Inc

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About Daniel Hsu

Hi there!

Listed skills include Eda, Physical Design, Vlsi, Algorithms, and 13 others.

Current workplace

Daniel Hsu's current company

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Ambarella Inc
Ambarella Inc
Sr Manager, DFT
AeroLeads page
9 roles

Daniel Hsu work experience

A career timeline built from the work history available for this profile.

Sr Manager, Dft

Current

Santa Clara, Ca, Us

Jul 2024 - Present

Sr Staff Dft Engineer

Santa Clara, Ca, Us

Sep 2023 - Jul 2024

Staff Dft & Design Engineer

Santa Clara, Ca, Us

Jul 2021 - Sep 2023

Senior Dft And Design Engineer

Santa Clara, Ca, Us

Jan 2019 - Jan 2022

Senior Backend Engineer

Santa Clara, Ca, Us

Jun 2018 - Jan 2019

Backend Engineer

Santa Clara, Ca, Us

VLSI chip implementation. Physical design focus. Advanced process (10nm and 14nm) experiences. ISO26262 functional safety training certified as "exida Functional Safety Practitioner". - Full responsibility of physical verification flow and execution - Cross domain knowledge and experiences to bridge gap between front-end and back-end - Chip-package-board co-design experiences - Lead and coach junior member to develop skills and responsibility

Jul 2015 - Jun 2018

Senior Engineer

Hsinchu, Taiwan, Tw

Test-Chip Design Department*** Test-chip design and implementation for the most advanced technology - RTL coding - Memory BIST - Synthesis - DfT design, ATPG - Silicon binning IP - Physical design - Timing signoff, P&R - Silicon to simulation correlation

Aug 2011 - Jul 2015

Internship

Hsinchu Science Park, Tw

Design flow and methodology division: - RDL router - Chip/package/board co-design

Oct 2010 - Jul 2011

Internship

Awb-Accton Wireless Broadband Corp

IR/EM analysis

Jun 2008 - Jul 2008
3 education records

Daniel Hsu education

Master'S Degree, Electronics Engineering

National Chiao Tung University

Master'S Degree, Embedded Systems And Industrial Informatics

Paris-Sud University (Paris Xi)

Bachelor'S Degree, Electronics Engineering

National Chiao Tung University
FAQ

Frequently asked questions about Daniel Hsu

Quick answers generated from the profile data available on this page.

What company does Daniel Hsu work for?

Daniel Hsu works for Ambarella Inc.

What is Daniel Hsu's role at Ambarella Inc?

Daniel Hsu is listed as Sr Manager, DFT at Ambarella Inc.

Where is Daniel Hsu based?

Daniel Hsu is based in Santa Clara, California, United States while working with Ambarella Inc.

What companies has Daniel Hsu worked for?

Daniel Hsu has worked for Ambarella Inc, Tsmc (Taiwan Semiconductor Manufacturing Company), Guc (Global Unichip Corp.), and Awb-Accton Wireless Broadband Corp.

How can I contact Daniel Hsu?

You can use AeroLeads to view verified contact signals for Daniel Hsu at Ambarella Inc, including work email, phone, and LinkedIn data when available.

What schools did Daniel Hsu attend?

Daniel Hsu holds Master'S Degree, Electronics Engineering from National Chiao Tung University.

What skills is Daniel Hsu known for?

Daniel Hsu is listed with skills including Eda, Physical Design, Vlsi, Algorithms, Interpersonal Communication Abilities, Timing, Accounting, and Semiconductor Industry.

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