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LEADERSHIP STRENGTHS• 9+ years of technical management experience leading a team of high-performance silicon validation and debug engineers responsible for pre-silicon readiness planning, post-silicon bring-up/validation, initial production, and post-launch sustaining support• 4 years of cross-organizational process improvement work as Collaborative Test Approach (CTA) architect accountable for improving post-silicon validation plans and enhancing test processes using the industry standard phased validation concept (bring-up, unit test, integration test, system validation test) to better enable collaboration amongst AMD’s geographically-diverse teams in developing and executing post-silicon validation plansTECHNICAL EXPERTISE• 5 years of hands-on Server and Embedded Lab experience as Lead System Engineer responsible for System and Silicon Validation/Debug of AMD Enterprise products • Excellent debugging skills at SoC and system level and strong experience with computer architecture concepts and silicon features• 10+ years of experience as silicon/platform validation and debug engineer with technical expertise in x86 SoC microarchitecture, x86 platform architecture, Server Operating Systems (Linux, Windows, Virtualization/Hyper-V), BIOS/FW Software Stack, Memory subsystem (DDR3/4), and Industry Standard high-speed interfaces (PCI-Express Gen3/4, SATA, USB)• Strong analytical skills in analyzing failures & identifing root-cause for SoC/APU uProcessor, Industry Standard High-Speed interfaces, Chipsets and System failures including x86 Core RTL Logic, Legacy/UEFI BIOS, Operating Systems, Signal Integrity, and System Stress Applications using comprehensive set of debug tools such as Logic Analyzers, JTAG/HDT Debuggers, Kernel Debugger, Scripts, and Scopes
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Manager - Memory Program And StrategyIbm Aug 2019 - PresentArmonk, New York, Ny, Us -
Senior Manager / Pmts – Server Silicon Validation And Debug TeamAmd Jan 2015 - Aug 2019Santa Clara, California, Us• Managed a high-performance technical team with 20+ engineers and contractors by focusing on building a highly effective silicon validation and IP debug team through mentorship and coaching core competency skills and debug methodologies• Drove cross-organizational lessons-learned from past projects in developing and implementing 20+ post-silicon validation improvement initiatives for future programs• Responsible for resource planning and ongoing risk versus priority adjustment to ensure that post-silicon validation execution and debug-resolution for gating issues would support the aggressive Silicon tape-out/IP schedule and multi-phased Software Stack BIOS FW Release schedule -
Pmts Lead System Engineer – Server/Embedded Platform EngineeringAmd Jan 2009 - Jan 2015Santa Clara, California, Us• Accountable for coordinating and prioritizing cross-functional execution and debug resources globally in executing aggressive Cross-Organizational detailed workflow plans to provide Silicon/System coverage for production GDS-O risk-call and initial production releases.• Develop pre-silicon readiness and post-silicon plan to validate specific IPs/functional blocks within the SOC (covering both functional operation and electrical characteristics)• Led cross-organizational technical teams in successfully developed and executed plans to validate Server/Embedded SoC & Software Solution
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Silicon Validation Cross-Organizational Process Improvement ArchitectAmd Jan 2005 - Jan 2009Santa Clara, California, Us• Collaborated with x-org technical leaders in developing the concept of Collaborative Test Planning (CTA) & Improving the AMD CTA process to align with the Industry Standard Phase Validation approach; thus, enriching x-org collaboration in developing complex silicon and software validation plans to ensure a robust System Solution in ramping Customers and then launching AMD Server Hydra product - Industry first x86 64 MCM in early 2009.• Led cross-organizational team in analyzing Post-GDSO and Post-IP Customers Launch-Gating problems then Developing & Driving implementations to improve pre-silicon readiness and post-silicon validation strategy as well as execution plans.• Worked with cross-organization teams for post-silicon validation readiness to ensure that Silicon/SW/Platform features enablement are aligned, Development Plans are prioritized/resourced, and Validation timeline would support production schedule.
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Server/Desktop Silicon Soc System Validation And Debug EngineerAmd Jul 1995 - Jan 2005Santa Clara, California, Us• Worked closely with Silicon Architecture, Platform Design, BIOS Developer, and Validation teams in successfully validated, resolved gating issues, and supported launching of multiple Server/Desktop SoCs including AMD K8 Hammer in 2005 (First x86 64 with Integrated UMC and HT Hyper-Transport Bus), AMD K5 / K6 / K7 x86 IA32 in 1996 through 1999. • Led complex debug efforts in identifying root-cause and verified resolution to support internal validation execution teams for Desktop and Server AMD x86 SoC/APU products. • Supported customer debug of complex issues for Server AMD x86 SoC through brainstorming, in-lab experiments, data analysis, and verification of final resolutions. • Analyzed & Identified root-cause for SoC/APU uProcessor, SATA, USB, PCI / PCIe-Gen3 Chipsets and System failures including x86 Core RTL Logic, Legacy/UEFI BIOS, Operating Systems, Signal Integrity, and System Stress Applications using comprehensive set of debug tools such as Logic Analyzers, JTAG/HDT Debuggers, Kernel Debugger, Scripts, and Scopes. • Debugged OS/Application level failures using Microsoft and/or Linux Kernel Debugger.• Collaborated with cross-functional team in developing HW/SW tools to improve SoC Debug timeline (Days-To-Solve)
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Silicon Validation Co-Op EngineerAmd Jan 1993 - Dec 1993Santa Clara, California, Us
Huan Le Skills
Huan Le Education Details
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National Technical University (Ntu)Computer Engineering -
The University Of Texas At AustinElectrical And Electronics Engineering
Frequently Asked Questions about Huan Le
What company does Huan Le work for?
Huan Le works for Ibm
What is Huan Le's role at the current company?
Huan Le's current role is Manager - Memory Program and Strategy at IBM.
What is Huan Le's email address?
Huan Le's email address is hu****@****ibm.com
What schools did Huan Le attend?
Huan Le attended National Technical University (Ntu), The University Of Texas At Austin.
What skills is Huan Le known for?
Huan Le has skills like Cross Funtional Team Leadership, Engineering Management, Test Planning, Linux, Perl, Ia32, Pcie, Managing Technical Personnel, Debuggers, X86 Uarch, Pcie Exerciser, Usb.
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