Hui S. Email and Phone Number

Doing both verification and design

(1) MLU SAT Verification (UVM & SystemVerilog) (Apr 2017-Sep 2017)• Bring up MLU SAT. Work closely with designer and partners to development components in existing environment and debug failures in nightly regression. • I am mainly working on Virtual Sequencer/Sequence, internal packet, TID manager, Scoreboard, Interface Checkers. • Design test cases in random regression, deliver diags to accelerate bringup progress, implement new packet format, PIO transactions, review testbench files and implement checkers/scoreboard for bug hunting.(2) L3 Cache BFM SAT Verification (VMM & SystemVerilog) (Aug 2016-Present)• Review and revised previous version of testbench files. Maintain a twiki page to help the follow-ups• Maintain and update of the L3 BFM testbench to verify the new feature implementations of RTL• Develop/Update Stub for RTL changes, such like UI and AXI interface changes.• Follow up random regression failures(3) Protolink Implementation for FPGA (Jan 2016-Aug 2016)• Setup and maintenance of the protolink flow • Work with third party companies to resolve tool bugs, such like ProtoRun ECO mode support; produce minimized design for Vivado settings debugging.(4) CLX/MCX SAT Verification (UVM & SystemVerilog) (Oct 2014-Aug 2016)• Review CLX/MCX Micro-Architecture Specifications, design and create test plan• Build testbench environment, develop UVM-based components and complex checkers• Develop constrained random test cases for CLX functionality verification• Maintain nightly and random regression for bug hunting• Create test matrix, support to develop SVA checkers and functional coverage objects• Use simprofile to check and improve bench performance (5) Test tool and library updates across all SAT platforms using rumor (Feb 2015-Dec 2016)

(1) Participating in hardware architecture design of new products. Doing research of state-of-the-art products and collecting relevant documents and datasheets of products to support our designs.(2) Cooperating with other engineers to design or redesign circuits and modules, such as TPM, 3G modems, keyboard. Drawing the schematic diagrams, time sequences and flowcharts. (3) Participating in prototyping, performance testing and debugging to better satisfying customers’ requirements.(4) Excellent intern of Intel Asia Pacific Research & Development Ltd, 2012.(5) Volunteer in Intel Volunteer Group