Chip verification:Fuse verification / Timing analysis on multi modes and cornersATPG works on millions SCAN FFs chips fabricated by TSMC from 28nm to 7nm (5+ chips taped out)- pre-atpg verification, including dft clocking structure / boundary signals behavior / test setup sequence- Serdes / compressor (mux & prpg/misr based structure) / scan chain verification- pattern generation / low coverage analysis / x-signal analysis- pattern simulation / on-site ATE bringup / shmoo hole debugProject leading experience:Leading 3 people to develop low test cycle pattern generation method- Invented "SPR" and "E-class" algorithm For both stuck-at/transition patterns, test cycle can be reduced by 5%-30% with all other qualities (coverage, power etc.) remain the same 15 IPs in 3 chips have been verified, using 12nm/7nm TSMC nodes- develop a fully automated ATE verification flow- develop a automated debug platform for chip verification

A meal kit delivery service company in Taiwan, like Blue Apron (NYSE: APRN) in US.We delivered over 10000 meal kits from 2016 APR to 2018 JUNE.As a co-founder and a major founder, below are my key achievements:- Product prototype design and test. Product structures design as roots for each product line- Product pricing strategy design, EX: Freight expense is reduced by 70% without any revenue loss- Design product manufacturing SOP and managing product delivery department. Labor expense is reduced by 60% compared to its peak value.- Co-branding partners exploration and negotiation. - LOTS of misc items

Full-time internship as a software engineer. Mainly working on enhancing and maintaining a commercial tool "Visual Signal", which is a GUI solution to time-frequency analysis (Using C#).