Hung Luu Email & Phone Number

With over 15 years of experience in hardware engineering, I am a seasoned leader and expert in SoC design implementation, timing closure. As a Senior Hardware Engineering Manager at Cadence Design Systems, I oversee the implementation of high performance ASICs for various clients and applications.My mission is to deliver quality, efficiency, and innovation in every project I manage or contribute to. I work closely with the backend design team to provide guidance and feedback on floor-planning, clock, and placement strategies. I also develop and optimize synthesis, LEC, STA and functional ECO automation flows . Additionally, I have co-invented a patented tiled datamesh architecture that minimizes latency and maximizes performance in interconnecting processors. I am passionate about solving complex and challenging problems in hardware engineering and creating value for my team, clients, and company.

Listed skills include Soc, Static Timing Analysis, Timing Closure, Asic, and 9 others.

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  Hochiminh University Of Natual & Sciences

  Telecomunication-Electronic