02/2006 - 02/2008: working for Greystone Data System Viet Nam as a Logic Design Engineer03/2008 - 02/2010: working for Greystone Data System Viet Nam as a Senior Logic Design Engineer03/2010 - 12/2010: working for Greystone Data System Viet Nam as a Senior Logic Design Engineer, DVT Team Leader and Vice R&D Hardware Manager01/2011 – 10/2015: working for AMCC Viet Nam as a Senior Verification Engineer11/2015 – 12/2017: working for AMCC Viet Nam as a Staff Verification Engineer01/2018 – 05/2023: working for Ampere Computing as a Staff/Senior Staff Verification Engineer06/2023 – Up to now: working for Quest Global VN as the Design Verification ManagerDV Experience Summary:- Experienced in various System IP, serial interface IP (SATA, USB, LDVS, ADC, DSP, UART, I2C, I3C, AVSBus, SPI, AIB, Generic Timer, Watchdog Timer…)- Experience in complete verification cycle from design concept to tape-out.- Build DV Environment (UVM Methodology), generate testcases, debug failures and improve/evaluate Functional Coverage, Code Coverage.- Experience in SoC/Fullchip Level and Block/IP Level verification.- Experienced in various ARM bus arch: AMBA (AXI, AHB, APB).- Experience in RTL Simulation and Gate Level Simulation (including SDF).- Experience in making the test-plan for IP Level and SOC Level.- EDA/Simulator: VCS/Verdi, Questasim/ModelSim, Xcelium/Simvision.- Programming skills: Verilog, SystemVerilog, UVM, C/C++