- PCIe Gen6 verification - NVMe IP verification + Improve env for faster simulation. + Creating test cases for covering new functions.- HWLL IP verification (build env, test case, S.B and test plan)

-Build SystemVerilog environment for SAS(Link + PHY layer), check coverage and SVA.-Build top chip verification environment for ASIC project for RTL verification/Nelist verification and SDF verification.-Technical support for NVMe verification.

Design Role:+Define topology for MCi matrix and AXI matrix.+Design AMBA NIC400 interconnect by using AMBA designer tool.+Doing synthesis, check LINT/LEC/CDC for released netlist.+Release SDC to the PnR team and work with them for high speed data path timing fix.Verification:+Doing verification for NVMe, PCIe(EP), DMAC, MCi, AXI matrix, SPI+Define verification plan for verified IPs.+Build UVM environment, scoreboard, SVA. Create test cases, random constraint and coverage check.+Work closely with IP designer for bug check.

Design Role:+Integrated/design cross-chip interface (MCi) to Amada chip. This is the first chip that can work with MCi.+Doing synthesis, check LINT/LEC/CDC for MCi netlist.+Work closely with the PnR team and STA member to fix high speed data paths (1Ghz clock operation).Verification Role:+Define verification plan for MCi design.+Build TB (UVM base), scoreboard, create test cases and check functional coverage.+Work closely with the IP design team for MCi verification.+Work closely with the validation team to validate MCi design on board.Achievement:+Receive “Marvell’s top 100 engineers” award from CEO.

Design Role:+Propose modification plan and make RTL for data cache improvement.+Define DMAC architecture (how many channels of DMAC, Peri-DMAC, how to connect) based on SoC specification.+Cooperate to IP in charge engineers to define AXI matrix architecture and generate RTL.+Doing synthesis, check LINT/LEC/CDC for AXI matrix design, DMAC, L3 cache.Verification Role:+Define verification plan for bus matrix and DMAC subsystem.+Build block level environment for AXI matrix and DMAC verification with SystemVerilog (AXI master/slave, checker, scoreboard).+Write ARM C-base code/Assembly code to verify DMAC/L3 design on SoC level.+Provide support to other team members for debugging ATE patterns. Achievements:+Silver award for first whole chip project (from RTL to PnR tasks were done in VietNam team). In this project, I play a role as bus matrix leader.+Gold award for IMR design (it can support full HD). In this design, I proposed a modification plan to improve cache performance.

Design Role:+Design and implement RTL based on bus matrix spec (Shwy (Hitachi internal bus/async bridge/sync bridge)) from Japan site.+Doing synthesis, check LINT/LEC/CDC for released netlist.Verification Role:+Define verification plan based on design specification.+Build block level environment for bus matrix/bridge verification (using systemverilog for building master/slave model, checker and scoreboard).+Cooperate to IP in charge engineers to debug failed cases on SoC and performance test.