As a layout engineer responsible for designing and optimizing the physical layout of analog circuits and systems, including floor planning, power routing, and signal routing. Conducting layout verification and analysis to ensure that the design meets the specified requirements and standards.The following projects were successfully delivered:Cadence Project on Intel 1.8nm: Working on PLL sub-blocks viz., CP, PFD, PLL LDO ,BGR with EMIR, ANTINNA, missing via, EXCEL Compliance checks.TSMC 6nm UCIE Project: Worked on RX sub-blocks.Design and Development of USB4 in 40nm SMIC Technology: Worked on layout RX_AFE blocks using Cadence Virtuoso layout editor, Calibre (LVS/DRC/PEX Tool). Blocks Worked on: Rx LOS Circuits, CTLE High Current Gain Stage, 2stage, 3stage amplifiers, equalizing resistor and capacitor blocks with EMIR calculations, termination blocks and other Sub-blocks of AFE, LFPS Sub-blocks, complete ownership of fb amps used in replica biasing, Rx AFE digital logic blocks with power grid connections10GHz Sardes Project for Intel: Worked on Tx side on 10nm for Intel. Responsibilities include: Nand, Nor, Latches, Inverters of different drive strengths with standard cells, 4-1 mux and 5 to 1 mux with dcaps in Tx side with cloning.22FDX, 12nm Training: Worked on std cell layouts of all the basic digital blocks. Analog design of comparators, Op-amps, BGR with planar and finfet technologies. Custom layout training done in IC connections on 28nm CMOS technology using Cadence Virtuoso and Calibre extraction tools. Learnt basics of semi- conductor technology and layout concepts. Worked on layouts of ADC amp, LDO with NMOS pass transistor and a parallel power switch, BGR, Comparator and RF blocks.