Define and co-design system architectures based on HPC and AI workloads performance modeling. Lead and participate in the development of novel methodologies for performance prediction dedicated to system designs, using real-life applications and standard benchmarks, including methods from cycle-accurate and up to high level approximations of the Compute and Communication phases to demonstrate the values of possible designs in terms of power and performance.

Directed development of the new methods, both “classic” and AI-assisted, for performance modeling of CPU and dGPU. Evolved analytical (fast) and cycle-accurate approaches to performance estimations and achieved company-wide adoption. Designed and published on internal GitHub tools for HPC/AI workloads runtime repeating patterns analysis and regions of interest identification and labeling.

Created and became a manager of a team of 7 talented software engineers handpicked for research and innovations in areas of HPC, SW optimizations, Performance Modeling targeted both CPU and dGPU, micro-architecture improvements, new CPU instructions inventions, visual performance analysis, automatic performance tuning and many more. Nurtured the talents and enhanced the skills of the team members who are now taking lead roles both within and outside the company. Co-Authored 4 patents.

Using my previous experience and deep knowledge of HPC applications, Compilers, Libraires and Profilers improved company Data Centers SW/HW by regularly preparing HPC applications performance and bottleneck analysis and working with the architects to address the issues. Proposed new instructions, micro-architecture improvements, software optimizations. Led pre-Si enabling of HPC WLs for AVX512. Developed and deployed methodology for performance modeling of HPC clusters targeted to future Intel architectures and used in various RFP technical responses. Co-Authored 9 patents.

Transferred to a newly created team with primary focus on HPC deals technical support. Directly worked with key HPC OEMs, like SGI, HP, DELL and continued to consult Shell in their seismic applications optimizations. Contributed to a numerous multi-million wins with Intel Architecture.

As a part of Compilers team was responsible for floating-point operations optimizations for Intel Itanium CPU, including initial implementation of support for non-standard 82 bits floating-point data type. Consulted Shell’s engineers on optimization of their in-house seismic applications for Itanium CPU, resulted in 2X-5X performance improvement.