Design verification engineer for the High Voltage Controllers Group

Methodology engineer in the WW Design Automation group. Responsible for development and maintenance of Worldwide project setup and update tool, Cadence check and save flow, parasitic extraction and constraint tool, simulation throughput enhancement scripts, and general productivity enhancement tool development. I am also the primary point of contact for EDA/PDK issues for a large external customer.

Responsible for coordinating PDK and EDA support for our COT (customer owned tooling) engagement with a large EU-based customer, leading the Productivity Improvement Projects from (a forum for creating and distributing productivity boosting tools and flows to designers), supporting parasitic evaluation methodologies, and providing general scripting support for the design teams. I also was responsible for coordinating the monthly HVAL Brownbag sessions, developing a sql-based tool usage tracking system and a Cadence crash metric reporting web dashboard.

Worked on driving the development and deployment of a PDK quality flow to ensure that all deliverables are properly QCed in our design environment. Developed Static Parasitic Analysis Tool (patented). This tool is designed to allow designers the ability to specify parasitic constraints on the Cadence schematic views and seamlessly transmit these constraints to the layout team. The tool also allows the layout designer to automatically check that these constraints were met and to assist in troubleshooting any errors. This tool is deployed worldwide and is in use by multiple business units.Developed goaGUI tool. This tool to serve as a GUI interface for the TI Gate Oxide Analysis script (goa) for designers working in the Cadence environment. The tool provides an easy to use interface for the checker as well as adding several new features including corner analysis and cross probing.Drove the expansion of our gate oxide integrity checking tool to include new processes. Drove enhancements to the tool and flow to enable parallelization of oxide analysis. Provided code to perform the parallelization that was included in the final release. This led to an order of magnitude speedup of analysis for large circuits.Pioneered the creation of the first Wireless Skill/Perl code release module. Managed all releases and a diverse design team to fulfill all project requirements. The library now includes contributions from several TI business units and is in use at TI sites worldwide as part of the Artisan release.

Member of the systems integration team on DDG (Guided Missile Destroyer)modernization program. Preformed an analysis of current hardware systems, requirements for modernization, and generated design recommendations based upon my findings.