Євген Короткий Email and Phone Number

Expert in FPGA/DSP/SDRCreating DSP/SDR applications in pure HDL either with High-Level Synthesis (Matlab/Simulink HDL Coder, Intel DSP Builder, Xilinx System Generator). Examples of implemented devices: DDCs, DUCs, local oscillators, and mixers, FIR, IIR, and CIC filters, fractional resamplers, Farrow structures, multichannel TDM implementation for filters and other processing blocks, PFB channelizers for thousands of channels, analog, and PSK modulators/demodulators, AGCs in time and frequency domain, circuits for phase, frequency and timing synchronization, supersampled processing, spectrum analysis, streaming STFFT/ISTFFT, time->frequency->time processing), AoA estimationCreating FPGA based digital systems & SoCs, including Linux driver development and high-speed interfaces (PCIe, 10G Ethernet, JESD204b, etc)Qualification: 1. Digital Design - expert level. Ready to implement any algorithm in hardware for FPGA/ASIC. Deep experience in HLS with Matlab HDL Coder and Intel DSP Builder2. Broad theoretical & practical background in DSP/SDR3. Verification - medium level. Able to write self-checking layered testbenches in System Verilog with SVA, random constraints, code&functional coverage, DPI, Python & Cocotb 4. SoC Creation - expert level. Experience with Intel FPGA Platform Designer (ARM, NIOS II) and Litex (RISC-V)5. Embedded programming - medium level. Experience with MIPS, ARM, RISC-V6. Embedded Linux & Linux drivers - medium level. Experience with Angstrom, Yocto, Buildroot, Debootstrap. Writing Linux drivers for ARM based HPS with FPGA hw accelerator, IRQs, DMA7. Digital Interfaces with FPGA - expert level. Experience with implementation and proper constraining ADCs, DACs, PCIe, 10G Ethernet, SPI, UART8. Tools for Digital Design: Quartus Prime, Vivado, Symbiflow, Cadence RTL Compiler & Encounter9. Tools for Digital Simulation: ModelSim, QuestaSim, Verilator, Incisive, cosimulation HDL with models in Simulink10. Tools for DSP/SDR: Matlab/Simulink, Python, GNURadio, GQRX