Iman Abdo Email & Phone Number

United States

Senior Principal DV Engineer (ASIC and FPGA) Lead Verification Engineer for NanoSemi/Maxlinear’s flagship DPD (digital pre-distortion) IP, for both ASIC and FPGA. Created the development environment for FPGA designs(C/C++/Verilog environment(DPI-C)), including setting up linux machines, installing tools and the automation scripts. Collaborated with the.

Worked as individual contributor and verification lead on multiple projects with many clients, covering block and system level verification and development of verification environment, with an all local team as well as an international one. I’ve also led the verification methodology development and have served as a guide and teacher for all new members of.

Austin, Texas, US

• Responsible for creating the environment and test plan to verify Hypertransport and DMA interfaces (which communicated with all the other peripherals).
• Served in system level solutions for data checking and scripting.
• Utilized in-house tools for environment management and commercial tools use, including Vera, VCS, Perl, Debussy and Verilog.

• USB Device and host verification in a C/C++/VHDL environment at the block level, as well as in a Vera environment at the system level. The System level consisted in an ARC configurable processor instantiated along with.
• Worked on creating a test plan
• Designing and coding a Vera environment for the verification of the SoC consisting of the processor and the peripherals around it.
• Used ASC tools for VHDL/Verilog translation and MTI simulation tools.
• Developed random test environment, Vera Generators, Monitors, protocol checkers and OVA assertions..
• Monitored performance and protocol errors.

• Bridge Verification
• Designed and coded a verification environment around a bridge device
• Wrote the test plan.
• The environment consisted of Vera Monitors, generators and both directed and random tests, around a Verilog design.
• A 3d party Verilog module was used with Perl, Makefile and shell scripts around it.

Dorval, Quebec, CA

• Member of the verification team in charge of the graphic processor and its sub-blocks.
• Worked in C / VHDL environment
• Developed C library to generate test vectors
• Assumed responsibility for behavioral models in the test bench environment including memory behavioral model which implemented DDR / SDRAM / SGRAM functions and a PCI behavioral model.
• Worked on scripts in shell and perl used in the environment and by the TransEDA coverage tool
• Performed some design synthesis using DC Compiler.