Iqbal Mahmud Email and Phone Number

- Manage R&D projects to drive device, circuit and product/IP level Gox/ILD-High Voltage/Aging/Electromigration/LU reliability, design rule, and method improvements.- Develop and implement reliability lifetime modeling with pre/post Si design/performance trade-off, and handle customer issues in reliability electronic design automation (EDA) industry tool flows.- Drive design collateral (PDK) delivery and reliability design technology co-optimization (DTCO).- Guide internal IDM and IFS foundry SoC/IP design teams along with EDA tool vendors (Synopsis, Cadence, Siemens, Ansys) for reliability flow/feature enhancement.- Ensure testchip/products design for reliability (DFR) with optimized PPA (Power, Performance and Area).Achievements: Received TD Excellence (Oct 2024), Q&R Divisional Recognition Award (Sept 2024), Design Enablement Team Award (April 2024) and multiple awards in 2023 for new reliability TFM enablement and internal/external customer reliability issue resolution.

> Reliability of 7nm, 14nm and 22 nm FDSOI process technologies across global fab locations.> Leading technical assessment activity for advanced technology development. > Wafer level reliability assessment on 3D FINFET, and physical models to estimate transistor lifetime.> Design of experiments and analysis methods for early reliability prediction.> Define and validate test structure design/layout for reliability test/characterization.

>Device Reliability for Intel's latest technologies.>Reliability test design and characterization.>High volume manufacturing test data analysis and correlate to device reliability.>Reliability risk assessment for process changes, quality and yield improvement & excursion management>Develop and coordinate quality systems to apply in different Intel factory sites across the world.>Technology transfer certification to high volume sites.

1. Device physics analysis for new ESD design concepts and their experimentation.2. Failure analysis and robustness characterization for several analog ESD technologies.3. Design optimization through correlating DC leakage behavior with bidirectional TLP measurement results.