Isaac Jan Email and Phone Number
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14 years’ experience in IC. design house as testing engineer, strong knowledge in testing methodology/hardware development/tracing issue analysis ability. 5 years’ experience in leading project and coordinate with cross function and co-work with external parties. Familiar with object oriented test programming, completed various test program implementation to win Samsung, NOKIA, Google, HP, Lenovo with excellent technical support. 8 years’ experience in Sensor and peripheral integration design application and troubleshooting. Innovate optronic calibration method to applicate for a patent in 2012, as well as designed board level tester in Synaptics to implement with worldwide manufacture, spending cost is lower than traditional solution over 50%. I able to work individually and under pressure to take on challenges, highly proactive but prudent personality results in innovation and risk management working style. Friendly and responsible with fast learning ability. Passion for learning new technology for constant improvement.
Synaptics Incorporated
View- Website:
- synaptics.com
- Employees:
- 857
-
Staff Testing EngineerSynaptics Incorporated Nov 2016 - PresentTaipei- Key Responsibility: FT/MT/In system testing(IST) of capacitive finger print I. Designed schematics of test interface/evaluation board of finger print sensor, provided proper solution for production/worldwide engineering usage II. Provided test plan and test strategy to give the best coverage and yield improvement for CM and independent hardware vendor(IHV) . III. Supported product verification, failure analysis, and yield improvement for HP/Lenovo.IV. Project management of testing related practice from initial stage bring to production execution stage, response for execution and monitoring task progress , coordinating with cross function and external parties.V. Joined and won the first in the world of under 200um glass finger print + touch pad hybrid solution for HP Brave NB.VI. Designed multi-sites board level strip tester for BGA & LGA scale process, as leader to manage project with cross function, and coordinate tester design and testing strategy with production planner , recently tested quantity is over 1KK/month, spending cost is lower than ATE + handler solution over 50%, per unit test time is almost same. -
Senior Product EngineerHycon Technology Corporation Jul 2015 - Oct 2016Taipei- Key Responsibility: CP/FT of EEPROM/Flash/Touchpad/MCUI. According to R&D designed IP to develop testing source bench and validate electrical characteristics on different platform ie. ATE(Chroma 3360/3380, V50, TR6850) & Labview + Instrument meter.II. Utilize C/C++/Python languages to develop application tool kit (Test pattern generator/test limit auto tracer...etc ). III. Codes development and operation, test program optimization and test time reduction. Statistical analysis with Quality Engineer and drive CM continuously improvement.IV. Assist Quality Engineer to identify all kinds of related issues and provide failure analysis experience and comments.VI. Supported failure analysis and FACR/RMA, resolved production stuck issue request 90% within 24 hours and 100% within 48 hours. -
Senior Test EngineerOmnivision Technologies, Inc. Aug 2014 - Jul 2015Taiwan- Key Responsibility: CP of 16 million pixels CMOS Image sensorI. Co-work with Validation engineer to collect data and verify new algorithm implement in ATE platform( KYEC E320).II. Developed schematics on MEMS type probe card and provide experience to modify optical light source for CP environment.III. Assist development team to Implement/validate new testing platform for over 20 million pixels CIS with 3GHz super high speed MIPY3 communication. -
Staff Testing EngineerLite-On Semiconductor Corp. Aug 2006 - Aug 2014- Key Responsibility: CP/FT of Laser Mouse/optical Finger Print/Ambient Light/Proximity/Gesture SensorI. Assist R&D engineer to validate IP design and performance in early stage, and implement to internal testing environment (ATE or Labview + Instrument meter)II. Responsible for planning of project testing & manufacture from silicon startup to production stage.III. Statistical analysis with Silicone Process Engineer to identify and judge FAB relayed defect.IV. Developed the invention of light source with Auto-calibration/compensation to meet critical optronic testing scenario.V. Designed optical mechanism for optronic sensor of CP/FT.VI. Develop application hardware ie. Mother board/Socket board of ATE, LED drive board of light source, Probe Card, Evaluation Board for FAE.
Isaac Jan Skills
Isaac Jan Education Details
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Aeronautical Engineering
Frequently Asked Questions about Isaac Jan
What company does Isaac Jan work for?
Isaac Jan works for Synaptics Incorporated
What is Isaac Jan's role at the current company?
Isaac Jan's current role is Synaptics Incorporated Staff Testing Engineer.
What is Isaac Jan's email address?
Isaac Jan's email address is ij****@****ovt.com
What schools did Isaac Jan attend?
Isaac Jan attended National Formosa University.
What skills is Isaac Jan known for?
Isaac Jan has skills like 半导体, 嵌入式系统, C, C++, 印刷电路板设计, 测试自动化, Testing, Semiconductor Industry, Embedded Systems, Debugging, Board Layout, Manufacturing.
Who are Isaac Jan's colleagues?
Isaac Jan's colleagues are Eric Pham, Albert Lai, Srikanth Erugu, Leon Chen, David Garrett, Joe Chou, Ting-Jan Yang.
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