• Responsible for generating, compiling, and debugging power management tests such as, restart, suspension and shut down for servers’ platforms. • The owner of developing the scenarios for the power management tests in Cadence Perspec for Intel Server Platforms in the Pre-Silicon stage.• Built emulation models for three different projects of client platforms, emulating the functionality of the CPU and PCH in FPGAs arrays in the Pre-Silicon stage.• Responsible for testing the data… Show more • Responsible for generating, compiling, and debugging power management tests such as, restart, suspension and shut down for servers’ platforms. • The owner of developing the scenarios for the power management tests in Cadence Perspec for Intel Server Platforms in the Pre-Silicon stage.• Built emulation models for three different projects of client platforms, emulating the functionality of the CPU and PCH in FPGAs arrays in the Pre-Silicon stage.• Responsible for testing the data traffic in new memories technologies of DDR5 for servers’ platforms in the Post-Silicon stage. Show less

Thesis: Modeling and simulation of wireless communication channels for V2V environments.

Responsible for the design and implementation of a data calibration algorithm to control a hardware architecture of serializers and de-serializers. The algorithm was programmed in C language and was implemented on the Micro-Blaze soft Processor of a Xilinx FPGA.