• Collaborated in the design, development and tape-out of 16 GHz PLLs for Die-to-Die and 32G multiprotocol PHYs in sub 5nm tech nodes• Supervised power-grid and metal routing for high-speed IO clock signaling paths• Oversaw layout floor-planning to preserve the integrity of sensitive analog sub-blocks• Designed SerDes sub-blocks including high speed clock paths, clock dividers, phase detectors, charge pumps and ring oscillators• Guided layout engineers in preserving matching and noise integrity of analog blocks• Adept in voltage regulator design, power delivery, Electromigration/IR and Aging aware design flow• Skilled in noise/power design tradeoffs, transmission line theory, analog integration and system modeling • Proficient in static timing analysis using NanoTime and TCL/Python scripting for PLL loop modeling and noise assessment

• Defined systems level architecture and tests for a variety of aerospace power systems units• Heavily involved in mixed signal Spice simulations, schematic capture and PCB design • Created models for DC, Synchronous and Stepper electric drives along with the necessary controls• Assessed and tested several power conversion and DSP ICs to verify compliance with system design • Reviewed PCBs to identify sources of EM/signal integrity issues and proposed minimalistic solutions • Troubleshooted PCBs using standard lab equipment, and executed both manual and automated test plans • Worked closely with software and hardware engineers to program and test microcontrollers and FPGAs • Implemented various communication protocols including SPI, UART, I2C, Ethernet and CAN Bus• Reviewed existing PCBs and suggested cost saving design changes and component replacement options