Signal Integrity Engineer
Current
Dec 2024 - Present
AeroLeads people directory · profile
Ishita Gupta Email & Phone Number
Signal Integrity Engineer | DDR | LPDDR | GDDR | Power Integrity
at
Cadence
1 work email found
@intel.com
LinkedIn matched
✓ Verified August 2026
4 data sources
Profile completeness 100%
Current company
Role
Signal Integrity Engineer | DDR | LPDDR | GDDR | Power Integrity
Location
United States
Who is Ishita Gupta? Overview
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Quick answer
Ishita Gupta is listed as Signal Integrity Engineer | DDR | LPDDR | GDDR | Power Integrity at Cadence, based in United States. AeroLeads shows a work email signal at intel.com and a matched LinkedIn profile for Ishita Gupta.
Ishita Gupta previously worked as Signal Integrity Engineer at Cadence and Hardware Engineer at Intel Corporation. Ishita Gupta holds Master Of Science - Ms, Electrical And Electronics Engineering from University At Buffalo.
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Email format at Cadence
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{first}.{last}@intel.com
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Profile bio
About Ishita Gupta
Analog Engineer working at Intel. Perpetual learner. Analog Circuits enthusiast.As an Electrical engineering graduate student, I identify myself as a proactive and inquisitive engineer. With a background in electronics and electrical, I am well versed with circuit design, validation and testing.Working in Intel, I have been able to sharpen my skills in EDA tools including Cadence Virtuoso, ADE-XL Test Editor, Maestro tool, bench testing instruments, post-silicon validation and characterization of PLL's over PVT. I am adept in Reliability analysis (tools such as SCARF Aging) for analog/mixed signal blocks. I recognize my technical skills in the aforementioned tools along with knowledge of CMOS IC Design concepts such as Opamp, LDO, A/D converters, Phase locked Loops, Bandgap References.
Listed skills include Cadence Virtuoso, Very Large Scale Integration, Digital Electronics, Microcontrollers, and 43 others.
Current workplace
Ishita Gupta's current company
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5 roles
Ishita Gupta work experience
A career timeline built from the work history available for this profile.
Hardware Engineer
Hardware validation platform design for post silicon IP’s and Intel processors. Full scale project development from conception to fabrication, including requirement collection, project FUB classification, design, overseeing layout, fabrication and final debug and deployment. Project lead for Design validation platform for Intel process product. Experienced with project management in several interposer projects. Collaborated with multiple teams across multiple geos for IP ownership, debug, validation and deployment.
May 2021 - Dec 2024
Analog Engineer
Measurement and post-silicon validation of PLL’s using test equipment such as Signal Analyzer, Spectrum Analyzer, function generator, multimeter. Running Duty Cycle Analysis, Jitter Analysis, Power-supply characterization, DCO-range check, Dynamic Temperature range check, post-divider check, frequency correction check - performed over various process skews, analog/digital supplies and extreme temperatures. Used Python and MATLAB scripting for register dump and bit un-blasting to read registers associated with PLL lock, unlock. Performed circuit design modification to accommodate technology scaling and ran simulations over PVT for reliability analysis. Re-scripting SPF scripts to simulate various customer configurations of PLL input and output frequencies using Synopsys DVE tool. Performed Electrical Validation and characterization on PLL’s in several new Intel ASIC products.
Aug 2019 - Mar 2022
Soc Design Intern
Characterization of high-speed PLL, implemented in advanced technology. Performing power supply current characterization for PLL. Root cause analysis - deterministic jitter of PLL in frequency correction mode. Evaluate duty cycle error in critical clock/data path with Monte Carlo/transient PVT simulations.
Jan 2019 - May 2019
Intern
Designing and testing of the Face Detection and Recognition System, under the mentor-ship of senior scientists in Armament Research and Development Establishment (ARDE), DRDO, India. The project required programming of Raspberry Pi using Python and running the system using linux commands. Concepts of Principal Component Analysis and Haar Cascades were used to implement the system, which was tested for accuracy with large samples of data.
Aug 2015 - Jul 2016
2 education records
Ishita Gupta education
Master Of Science - Ms, Electrical And Electronics Engineering
University At Buffalo
Bachelor'S Of Engineering, Electronics And Telecommunication
Savitribai Phule Pune University
FAQ
Frequently asked questions about Ishita Gupta
Quick answers generated from the profile data available on this page.
What company does Ishita Gupta work for?
Ishita Gupta works for Cadence.
What is Ishita Gupta's role at Cadence?
Ishita Gupta is listed as Signal Integrity Engineer | DDR | LPDDR | GDDR | Power Integrity at Cadence.
What is Ishita Gupta's email address?
AeroLeads has found 1 work email signal at @intel.com for Ishita Gupta at Cadence.
Where is Ishita Gupta based?
Ishita Gupta is based in United States while working with Cadence.
What companies has Ishita Gupta worked for?
Ishita Gupta has worked for Cadence, Intel Corporation, and Defence Research And Development Organisation.
How can I contact Ishita Gupta?
You can use AeroLeads to view verified contact signals for Ishita Gupta at Cadence, including work email, phone, and LinkedIn data when available.
What schools did Ishita Gupta attend?
Ishita Gupta holds Master Of Science - Ms, Electrical And Electronics Engineering from University At Buffalo.
What skills is Ishita Gupta known for?
Ishita Gupta is listed with skills including Cadence Virtuoso, Very Large Scale Integration, Digital Electronics, Microcontrollers, Vhdl, Linux, Microwind Cmos Layout Design And Simulation Tool, and Xilinx Ise.
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