Hardware validation platform design for post silicon IP’s and Intel processors. Full scale project development from conception to fabrication, including requirement collection, project FUB classification, design, overseeing layout, fabrication and final debug and deployment. Project lead for Design validation platform for Intel process product. Experienced with project management in several interposer projects. Collaborated with multiple teams across multiple geos for IP ownership, debug, validation and deployment.

Measurement and post-silicon validation of PLL’s using test equipment such as Signal Analyzer, Spectrum Analyzer, function generator, multimeter. Running Duty Cycle Analysis, Jitter Analysis, Power-supply characterization, DCO-range check, Dynamic Temperature range check, post-divider check, frequency correction check - performed over various process skews, analog/digital supplies and extreme temperatures. Used Python and MATLAB scripting for register dump and bit un-blasting to read registers associated with PLL lock, unlock. Performed circuit design modification to accommodate technology scaling and ran simulations over PVT for reliability analysis. Re-scripting SPF scripts to simulate various customer configurations of PLL input and output frequencies using Synopsys DVE tool. Performed Electrical Validation and characterization on PLL’s in several new Intel ASIC products.

Characterization of high-speed PLL, implemented in advanced technology. Performing power supply current characterization for PLL. Root cause analysis - deterministic jitter of PLL in frequency correction mode. Evaluate duty cycle error in critical clock/data path with Monte Carlo/transient PVT simulations.

Designing and testing of the Face Detection and Recognition System, under the mentor-ship of senior scientists in Armament Research and Development Establishment (ARDE), DRDO, India. The project required programming of Raspberry Pi using Python and running the system using linux commands. Concepts of Principal Component Analysis and Haar Cascades were used to implement the system, which was tested for accuracy with large samples of data.