Asic Design Engineer
Skilled in Verilog-based Design Flow with more than 1 year of experience.Tested and Verified the Design functionality through simulators.Experienced in test plan creation, testcase development using SystemVerilog.Used design tools to Optimize the RTL Code and to improve the overall efficiency of the Design.Worked with other teams to develop the design with accurate implementation.Resolved Customer-reported issues through debugging and helped in the improvement of overall coverage.Ensured Design Quality and integrity by Linting, Spyglass and CDC.Good Understanding of IP Specification and Architecture.