C++ developer on a project of custom place and route tools development for Structured ASIC (eASIC) flow. Responsibilities: Support existing codebase, implement runtime and QoR optimizations, resolve bugs across multiple components, collaborate with Customer Engineering and Quality Assurance teams.Achievements:• Implemented several optimizations for net buffering algorithm to decrease leaf wire length by 40%.• Ported the buffering algorithm to a new device technology.• Performed bottleneck optimization that resulted in 5% runtime improvement.• Provided fast slack calculation to estimate a cell reconnection profit.Technology stack: C++, Python, TCL

C++ developer on a project of custom place and route tools development.

Senior Verification Engineer in a mixed signal designs laboratory.Responsibilities: Leading, planning and monitoring of the digital functional verification process of individual IP blocks and complex devices developed in the mixed signal designs department. Have been mentoring an intern to introduce him to an internal verification workflow.Achievements:• Fully designed and implemented a verification of digital parts of 2 ICs.• Developed a Boost.Python wrapper for ADC analog core model to perform fast mixed signal simulation.Technology stack: C++, SystemC, SystemVerilog, Python, TCL, Cadence NCSim

Verification Engineer in a mixed signal designs laboratory.Responsibilities: • Digital functional verification of IP blocks and ADC chips.• Development of verification environment and algorithms for test scenarios for RTL-models, writing functional models in C++ of data processing blocks: convolutional processors, blocks of decimation, filtering, correlation.• Implementation of drivers, data generators and monitors for interfaces: AMBA AHB, APB, SPI, JESD, SpaceWire. • RTL and gate-level simulation.• Programming and debugging of processor cores. • Analysis of functional coverage. • Collaboration with RTL and system level designers.Achievements:• Developed a set of complex test scenarios in C++/SystemC to verify ICs: ADCs and DSP processors. • Designed and implemented verification environment library of configurable components.• Implemented a software calibration algorithm for the tasks of validating manufactured IC (post-silicon validation) using spectrum analyzer’s API.• Developed a dashboard service for regression monitoring with Jenkins backend and Django frontend (Python).Technology stack: C++, SystemC, SystemVerilog, Python, TCL, Cadence NCSim

Trainee in a mixed signal designs laboratory.Responsibilities: • Programming of test scenarios for RTL design using the SystemC library and the API of the verification environment library. • Simulation of test scenarios, debugging and documentation of errors in the operation of the device under test.Achievements:• Performed a functional verification of SPI interface of several ICs. • Developed a visualization tool for verification components connectivity using GraphViz library.

I was engaged in software development of a CAD tool for the problem of technology mapping at the stage of logical synthesis in the FPGA design flow.Achievements:• FPGA LUT technology mapper was implemented in C language with TCL interpreter as a user interface.• A conference paper was written https://ieeexplore.ieee.org/document/7910595Technology stack: C++, TCL