J Srikanth Email & Phone Number

1. Hands on experience with floor planning, power planning, IR drop analysis, placement (congestion removal), cts, detailed routing fixing shorts, openings, DRC's.2. Hands on Floorplan such as Placement of macros and block ports. Placement of macros done by looking into their design hierarchy and flylines.3. Performed power plan and ensured that power pins are connectedHands-on experience in Synopsys ICC ll tool.Good knowledge in STA concepts and hand's-on experience.4. To meet IR drop target, changed the width, pitch, offset, specing values of metal wires respectively. And also performing quality or sanity checks at each implementation stage.5. Checking placement using legality checker and removing congestion by estimating required channel specing and also using different blockage or cell padding6. Understanding of design environment definitions such Process, Voltages and Temperatures. and familiar with design rule and optimization constraints such as tran,cap, speed,area etc.7. Analyzing clock tree at CTS to achieve minimum insertion delay and skew along with few clockDRV's and checking setup and hold vialations for different timings paths.8. Familiar with OCV, AOCV, CRPR and also haveunderstanding on detail routing. and post routing optimization techniques. And hands on with fixing shorts, opens, drc'c manually.9. Good knowledge on backend ASIC design flowand also basic understanding on synthesis (RTL2GDS) and low power techniques like power gating, multi VT techniques.