Jackey Q Email & Phone Number

Shanghai City, China

Take the lead role and responsible for creation and management for the hardware, Fpga and other technical project, identifying project process and/or system improvement opportunities, and driving solving method of the project issue for the future release. Support the guidence to R&D team both in internal R&D team and outside.Delivery the specialist designing solutions to the university teachers and some key customers.

Shanghai

•9 years in hardware and fpga designing in CETC.•R&DTeam manager of Digital signal processing in CETC•Good at FPGA designing , especially algorithm designing like intermediate frequency digital receiver,FFT,FIR in FPGA（SDR）•Know well about DSP hardware designing.•Proficient in emulation by matlab, good master of protel99, Altium Designer,tools of pcb designing •Expetise in vhdl,verilog,language c programming•Use FPGA designing tools like quartus II, dspbuilder, sopc ,ISE with skill.•Excelent communication skills including written,reading,verbal in English.•Know well about Management.

Education record

Education record