Jackson Chung Email & Phone Number

Mountain View, CA, US

• Leading and built a strong global team of engineering managers and technical staff (40+) in Hardware Design Validation, Signal and Power Integrity Simulation, PCB Design, Component Engineering, and Engineering Lab.
• Proven track record of team development and leadership development of successful next-level managers in a complex environment
• Founded the Hardware Design Validation team in Google Nest to enable high-quality design
• Drove Google's consumer hardware validation strategy and infrastructure development
• Led team to support all new Google Nest smart home hardware products:
• 2020: Nest Audio, Chromecast with Google TV, Google Nest Thermostat, Google Wifi

Cupertino, California, US

• Founding member of a team of 5 electrical engineers responsible for driving system hardware design validation to closure
• Covered all aspects of electrical system design validation, including planning, definition, methodology development, issue resolution, and status reporting to executives
• Involved in design optimization and review at all development stages of new product introduction (Prototype, EVT, DVT) and post-ramp qualification builds
• Products completed and released: iPhone 7 & 7 Plus and iPhone SE (2016), iPhone 6s & 6s Plus (2015), iPhone 6 & 6 Plus (2014), iPhone 5s & 5c (2013), iPod touch (2015)
• Defined, implemented, and scaled the validation process for all iPhone and iPod development programs. Process promoted to other hardware teams and implemented across Apple Watch, iPad, and Accessories due to its.
• Engineering Manager of 23 interns over 2 years. Provided mentorship and guidance to them in design and validation activities across multiple iPhone projects.

Milpitas, CA, US

• Designed four PCB daughter cards for testing next generation NAND flash memory modules including schematic capture and layout design
• Developed advanced test techniques and methodologies for next generation high-speed back-end flash memory interface
• Performed design validation on back-end flash memory interface, including validation of error correction coding (ECC) and signal integrity analysis of parallel data bus between various memory controllers and NAND flash.

• Advanced Characterization Engineer (July 2008 - February 2010)Characterization Engineer (May 2006 - June 2008)
• Performed new hardware infrastructure planning and evaluation for the 28-nm, 28-Gb/s transceiver test chip characterization
• Developed methodologies to characterize the intrinsic performance limits of high-speed transceivers
• Defined and coordinated design and layout optimization of test chip characterization board
• Evaluated performance of system interconnects including test socket, cables, and connectors
• Primary engineer responsible for characterizing Altera’s high-speed transceiver FPGAs, including Stratix IV GT (11.3 Gb/s), Stratix IV GX (8.5 Gb/s), and Stratix II GX (6.375 Gb/s)

• Performed semiconductor failure analysis on antifuse and flash based FPGAs manufactured on various CMOS process technologies
• Teleconferenced with customers regularly to discuss complex technical details, report case status, and provide recommendations
• Resolved 90 customer related failure analysis cases on Actel's FPGAs
• Wrote over 200 formal reports to customers
• Applied analytical tools such as micro-probing, photoemission, liquid crystal, FIB, SEM, CSAM, chemical deprocessing, and common lab equipment (oscilloscope, function generator, data generator, semiconductor parameter.
• Analyzed circuit layout and schematics using computer aided IC design tools

• Full-time internship (Professional Experience Year - PEY)

• Troubleshot and debugged consumer electronic products conforming to the customers' requirements
• Evaluated the reception performance of telecommunications products

Master Of Science (Ms), Electrical Engineering

Bachelor Of Applied Science (Basc), Electrical Engineering

Stanford Certified Project Manager (Scpm), Stanford Advanced Project Management Certificate (Sapm)

Master Of Science (Ms), Finance