Shaik Jaffar Ali Email & Phone Number

Bengaluru South, Karnataka, India

• Gained a solid understanding of digital design and verification methodologies, including coverage-driven verification aligned with V-plan.
• Acquired knowledge in regression automated testing using Makefile, Perl scripts, and testcases, utilizing SystemVerilog OOPS concepts.
• Learned essential skills like assertions, DFT techniques, CMOS basics, FPGA architectures, and static timing analysis (STA), soft skills.
• Developed a strong understanding of IP-level verification, basic understanding of SOC-level verification along with the entire RTL to netlist design and verification flow.

• Contributed to a Processor Design Project as a trainee, gaining hands-on experience in Design and verifying RISC-V processor architecture.
• Optimised the architecture to consume fewer clock cycles by implementing a hazard detection unit with a 50% improvement in speed.
• Implemented clock gating technique resulting in a 40% reduction in power consumption using Verilog HDL and Xilinx Vivado software.

Bachelor Of Technology - Btech, Electronics And Communications Engineering, 9.19 Cgpa

Activities and Societies: National Service Scheme• Researched under a professor, authoring 3 research papers, filing 2 patents and 1.

Intermediate, Mpc, 9.88 Cgpa

Matriculation, 10 Cgpa