Jagadeesh Pechetti Email & Phone Number

I am a Physical Design Engineer with experience in custom RDL routing, power analysis using PTPX, and EMIR verification. Over the past year, I have sharpened my skills in ensuring reliable chip design by optimizing custom routing workflows and performing power integrity checks to meet design specifications.In my initial role, I contributed to designing and implementing custom RDL routing solutions, ensuring efficient signal flow and layout optimization. Later, I transitioned to power analysis and EMIR validation, focusing on identifying and resolving critical power and reliability issues in advanced semiconductor designs.I’m passionate about learning new tools and techniques in the VLSI domain and contributing to high-performance, reliable chip designs.

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  Physical Design Engineer

  Tessolve

  Jan 2024 - Present - Bengaluru, Karnataka, India