Jagan John Email & Phone Number

Malvern, Pennsylvania, Us

Chandler, Az, Us

Worked on front end design, verification and Xilinx FPGA build/validation activities for a Single Port Ethernet Transceiver with support for both 100 and 1000 Mbits/sec capability on TSMC 40nm node. The focus for the product was low power consumption and optimized for automotive use cases.

Chandler, Az, Us

SoC Design -1. Lead a design team on a 48MHz security focused ultra-low power SoC design on UMC 110nm node. Being the design lead also extended my focus to other areas like design verification, synthesis, floor planning, DFT and packaging activities.2. Supporting FPGA build activities and develop validation testbenches to verify the design. Chameleon ProFPGA was the platform for FPGA builds.3. Worked on multiple 55nm, 90nm, 110nm, 180nm chips (ARM and MIPS processors) and IP designs projects starting from design planning phase, SoC design, verification all the way to stream out or RTP. Microcontrollers ranged from mid frequency (above 200MHz) to low frequency parts (48MHz) supporting a wide variety of applications including automotive.4. SoC / IP design, verification tests development, debugging failing tests (both RTL and Gates), lint, CDC, RDC, Static Timing Analysis (STA), scan runs are some of the daily activities involved with our design projects.IP Design -1. Designed a 50MHz Audio SPI controller IP with up to 8 channels focused mainly for Audio applications. FIFO design, logic for clock generation and requests, data shifting in and out, frame generation for Audio/Frame transfer in Host/Device modes are part of the IP design.2. Created USB2.0 OTG controller wrapper designed to work with 55nm Innosilicon USB2.0 PHY. Startup, clock request, suspend/resume functionalities, register access and extra logic for secure access to the PHY were designed and implemented inside the OTG module.Sustaining and validation activities –1. Working with multiple customers, field and application engineers to help analyze issues seen on-board applications involving Microchip’s MCU32 parts. Work involves root cause analysis, suggesting workarounds on software or customer boards, design fixes or issue errata.2. Supporting validation team with debug and clarification issues seen on streamed out silicon.

Chandler, Az, Us

Front End digital design engineer working on design, integration and testing of 32 bit microcontrollers.

Tempe, Az, Us

Financial Aid reporting activities and database management.

Bangalore, Karnataka, In

Bangalore, Karnataka, In

Masters In Electrical Engineering, Electronic And Mixed-Signal Circuit Design

Bachelor Of Technology, Applied Electronics And Instrumentation

High School