Jakob Jones Email & Phone Number

Mountain View, Ca, Us

Directing Operations and Programs for Google's Custom Silicon Accelerators for AI/ML/Networking/Video

Mountain View, Ca, Us

Leading several silicon and software engineering organizations to deliver ASIC / FPGA / IP / SoC products for data center in the areas of AI, video, and networking acceleration and general compute infrastructure.

Santa Clara, California, Us

Leading a multi-discipline engineering organization to deliver FPGA-based acceleration platforms for Cloud, Data Center, Military, and Embedded environments.

Santa Clara, California, Us

Managing a talented team of multi-discipline engineers to deliver FPGA-based acceleration technologies and platforms into the cloud and datacenters.

San Jose, California, Us

San Jose, California, Us

Manager for transceiver PHY IP team. Manage and mentor a team of talented engineers responsible for technical vision and leadership, product strategy, use model definition, and low-level development for Altera's transceiver IP. Cross group coordination to drive transceiver features and ensure usability at every level from silicon through customer IP. System level design, HDL design, embedded processor and software, IP development infrastructure design, hardware calibration algorithms and implementation.

San Jose, California, Us

Technical lead for transceiver PHY IP team. Responsible for technical vision, innovation, leadership, product strategy, use model definition, architecture, and low-level development for Altera's transceiver IP. Cross group coordination to drive transceiver features and ensure usability at every level from silicon through customer IP. System level design, HDL design, embedded processor and software, IP development infrastructure design, hardware calibration algorithms and implementation. Focus on scalable, re-usable, customizable solutions that must work without error across thousands of unique designs throughout the entire world.- Led cross-functional initiative for SERDES architecture simplification- Led and implemented complete re-design of Transceiver PHY product portfolio for Arria 10 and Stratix 10 series FPGAs- Led cross-functional introduction of Solution Architect Teams to ensure usability and collaboration across engineering organizations- Led and implemented several technology innovations in the areas of device architecture, IP development infrastructure and tools, processor based transceiver calibration, and embedded debug tools.- CTO office memberSkills / ToolsVerilog, C/C++, TCL, Perl, Modelsim, VCS, NcSim, Spyglass, MS Project.Serial protocols including PCI Express, 1G/10G/40G/100G Ethernet, Interlaken, SDI, Displayport, SATA/SAS, etc.

Montreal, Quebec, Ca

Design of video broadcast equipment. Technical lead and hardware architect for several products including Grass Valley's TMV (Trinix Multiviewer) product. Responsibilities include product research and architecture definition, technical team leadership, FPGA design, PCB design, software design, test and debug.Responsible for full hardware design and execution, product feature definition, board design, component selection, power supply design, FPGA design, software design, etc.ProjectsTMV - Trinix Multi-viewer - In-router multi-viewer system. 32-SDI input x 9-SDI output. Best-in-class system integration and power consumption. Responsible for product definition, design concept, PCB design, FPGA design, embedded software and driver design, board bringup. Led team of hardware engineers and closely collaborated with software team.TRIO - Triple-Rate Input/Output SD/HD/3G SDI signal generator / receiver. Responsible for entire design including PCB, FPGA, embedded software, and tools. 16-SDI inputs x 16-SDI outputs. Video processing, test-pattern generation, on-screen video display. Highly configurable platform designed for large-scale SDI system testing and demonstration.Trinix 3G router cardsJEP (Jupiter / Encore) control panelsSkills / ToolsFPGA design using Verilog, Modelsim, Xilinx ISE, Altera Quartus IIEmbedded software using C/C++, Xilinx MicroBlaze, Altera NIOS IISoftware tool design using C# and Java, Microsoft Visual Studio, NetbeansSimulation using Mentor Hyperlynx, PSpice, Modelsim.PCB design in Cadence Allegro, Concept HDL, Hyperlynx, LTSpiceAltera Stratix IV GX, Stratix II GX, Stratix III, Cyclone III. Xilinx Spartan II, Virtex IIInterfaces include Ethernet, SDI, DVI, VGA, LVDS, SERDES, SPI, I2C, SMBus, SDcard, DDR2/DDR3, Serial flash

Boise, Idaho, Us

Design of test equipment for DDR,DDR2 SDRAM and NAND flash memories. FPGA, PCB, and software design.FPGA design in VerilogEmbedded software design using C/C++Software tool design using JavaPCB schematic capture and board design using PCADImplemented complex algorithms for test pattern execution for DRAM and NAND flash parts.Implemented NAND flash controllers and testersImplemented complex runtime compression algorithms in Verilog. Prototyped and simulated in Java / C++Interfaces and protocols include PCIe, USB, I2C, SPI, DDR/DDR2, NAND flash, NOR flash.

N Logan, Ut, Us

Testing hardware and software for in-flight imaging reconnaissance systems developed for DODSecret level DOD security clearance

Master'S Degree, Electrical Engineering

Bachelor'S Degree, Electrical Engineering, Minor In Computer Science