Josh Mchenry Email & Phone Number

As a SOC/ASIC Verification Engineer with over 2 years of hands-on experience, I specialize in UVM testbench design, debugging, and verification of RTL designs. My passion lies in creating robust verification environments tailored to meet project requirements, seamlessly integrating with meticulous test plans and regressions.My expertise extends to a diverse range of serial protocols including USB, PCIe, SATA and application layers such as UAS, BOT, xHCI, and NVMe. I thrive in environments where intricate protocol understanding is essential, leveraging this knowledge to ensure thorough verification and validation of designs.