James Abel Email & Phone Number

Although I'm a VP, I mostly do technical work. Architected and developed a cloud (AWS) based product for the medical industry. I develop mainly in Python at this point (and some C/C++ where needed). The product uses a "cloud native" AWS implementation (S3, DynamoDB, SNS/SQS). Also PyQT5 and MATPLOTLIB are used in the production pipeline. Signal Processing.

Santa Clara, California, US

Hardware and Software architectures. Design Automation, Simulation, Modeling, Tracing, Optimization, Architecture Analysis, Application Analysis.

Santa Clara, California, US

Chief Tracing Architect responsible for the architecture and design of software workload ‘Tracers’. These Tracers take a software application workload and create a set of files that represent relevant execution information that is fed into CPU and full platform simulators for performance and power analysis.Led cross-Intel initiatives on Tracing and.

Santa Clara, California, US

Responsible for identification, acquisition and use of emerging workloads to improve the performance and/or power of future Atom cores, focusing on 2015+ product lines. Performs deep architecture and micro-architecture analysis both pre-silicon and post-silicon to identify improvements. Does path-finding and technical readiness analysis. Focus areas are.

Santa Clara, California, US

• Responsible for performance optimizations of key software applications, and uses these applications to improve Intel’s future processor and platform products. Works as a virtual member of the architecture and product.

Santa Clara, California, US

Responsible for performance optimizations of key software applications, and uses these applications to improve Intel's future processor and platform products. Works as a virtual member of the architecture and product groups, infusing software knowledge into Intel products. Drives key performance and performance/power improvements into Intel's processor and.

Santa Clara, California, US

Responsible for optimization of multi-media and signal processing applications. Major projects included implementation of a Dolby Digital decoder using MMX™ Technology (http://developer.intel.com/technology/itj/q31997.htm) and speech recognition programs. Also developer on Native Signal Processing/IA-SPOX project (signal processing OS that resided in a.

Santa Clara, California, US

Design engineer on a single-chip communications product. Responsible for interconnect design, as well as full-chip RTL models. This product targeted wireless communications, utilizing two DSPs and one microcontroller (80186 core).

Santa Clara, California, US

Responsible for behavioral models of embedded cores (8051, 80186) and other standard cells. Also responsible for software for automated test.

Designer of automated test systems. Targets included micro-processor based adapter boards, systems and SCSI disks.

Designer of single-board microcomputer systems based on the 68000 processor and Multi-bus for automated news services. Wrote low level networking drivers.

Master’S Degree, Cs

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