James Abel Email & Phone Number

Although I'm a VP, I mostly do technical work. Architected and developed a cloud (AWS) based product for the medical industry. I develop mainly in Python at this point (and some C/C++ where needed). The product uses a "cloud native" AWS implementation (S3, DynamoDB, SNS/SQS). Also PyQT5 and MATPLOTLIB are used in the production pipeline. Signal Processing and Machine Learning are used in the product "engine".

Santa Clara, California, Us

Hardware and Software architectures. Design Automation, Simulation, Modeling, Tracing, Optimization, Architecture Analysis, Application Analysis.

Santa Clara, California, Us

Chief Tracing Architect responsible for the architecture and design of software workload ‘Tracers’. These Tracers take a software application workload and create a set of files that represent relevant execution information that is fed into CPU and full platform simulators for performance and power analysis.Led cross-Intel initiatives on Tracing and SimulationUtilized machine learning techniques to select the most relevant aspects of the workloads.Lead and mentored a technical team of ~20 engineers in the areas of hardware and software architecture and design.Established engineering quality standards - code and design reviews, coding standards, test requirements (unit, system, regression).

Santa Clara, California, Us

Responsible for identification, acquisition and use of emerging workloads to improve the performance and/or power of future Atom cores, focusing on 2015+ product lines. Performs deep architecture and micro-architecture analysis both pre-silicon and post-silicon to identify improvements. Does path-finding and technical readiness analysis. Focus areas are media and DSP workloads.Analyzes industry standard benchmarks such as SPEC CPU, EEMBC FP and SysMark. Also analyzes ISV applications and workloads.Creates proposals for these improvements, evaluates the technical feasibility and negotiates with design, planning and software teams to get product buy-in. Establishes programming models associated with these features. Writes detailed technical architecture specifications.Utilizes proprietary tracing, simulation and analysis environments to model and analyze improvements such and new instructions and/or micro-architectural features. Utilizes core and platform behavioral models. Specifies and/or writes new tools required to perform these evaluations. Creates new analysis techniques and best-known-methods for performance and power analysis.Serves on corporate-wide technical committees to steer Intel’s architectural directions.

Santa Clara, California, Us

• Responsible for performance optimizations of key software applications, and uses these applications to improve Intel’s future processor and platform products. Works as a virtual member of the architecture and product groups, infusing software knowledge into Intel products. Delivers workload characterization, tracing and analysis to Intel’s processor and platform architecture groups. Performs pre-Si analysis in a simulation-based environment using both high level behavioral and RTL models. Gathers, root-causes and dispositions sightings of performance anomalies in key applications. Develops point tools for application characterization, tracing, simulation and analysis (both pre- and post-Si).Drives key performance and performance/power improvements into Intel’s processor and platform products (e.g. Intel® Core™ processor family and Intel® Core™ Atom processor). This includes co-owning and driving new instruction definition for HPC/multimedia/imaging/3D into instruction sets such as SSSE3-SSE4.1, AVX, as well as general micro-architectural performance improvements. Also drives performance improvements into Intel compilers.Selection and development of kernels, tracing, modeling new instructions in a proprietary simulator, participating in performance ‘dungeons’, and analysis and performance estimations of kernels/workloads. Provides speedup estimates of new instructions on kernels and workloads as well as input into the micro-architecture to improve the performance (and performance/power) of particular implementations.Also works with strategic ISVs to optimize their code for Intel Architecture as well as use this code for tech readiness.

Santa Clara, California, Us

Responsible for performance optimizations of key software applications, and uses these applications to improve Intel's future processor and platform products. Works as a virtual member of the architecture and product groups, infusing software knowledge into Intel products. Drives key performance and performance/power improvements into Intel's processor and platform products (e.g. Intel® CoreTM processor family and Intel® CoreTM Atom processor). This includes co-owning and driving new instruction definition for HPC/multimedia/imaging/3D into instruction sets such as SSSE3-SSE4.1, as well as general micro-architectural performance improvements. Delivers workload characterization, tracing and analysis to Intel's processor and platform architecture groups. Performs pre-Si analysis in a simulation-based environment using both behavioral and RTL models. Develops point tools for application characterization, tracing, simulation and analysis (both pre- and post-Si). Also drives performance improvements into Intel compilers.

Santa Clara, California, Us

Responsible for optimization of multi-media and signal processing applications. Major projects included implementation of a Dolby Digital decoder using MMX™ Technology (http://developer.intel.com/technology/itj/q31997.htm) and speech recognition programs. Also developer on Native Signal Processing/IA-SPOX project (signal processing OS that resided in a Windows driver).

Santa Clara, California, Us

Design engineer on a single-chip communications product. Responsible for interconnect design, as well as full-chip RTL models. This product targeted wireless communications, utilizing two DSPs and one microcontroller (80186 core).

Santa Clara, California, Us

Responsible for behavioral models of embedded cores (8051, 80186) and other standard cells. Also responsible for software for automated test.

Designer of automated test systems. Targets included micro-processor based adapter boards, systems and SCSI disks.

Designer of single-board microcomputer systems based on the 68000 processor and Multi-bus for automated news services. Wrote low level networking drivers.

Master’S Degree, Cs

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