James Chang Email & Phone Number

Santa Ana

FPGA development for ASIC emulation.

Costa Mesa, Ca

Technical lead of 3 FPGA engineers to emulate SoC ASIC designs in different phases. Delivered logic and timing accurate FPGA builds to accelerate hardware and software development.• Emulated at least five ASIC chips successfully on time, up to 50M gates size, consisted of high-speed serial links. Ensured ASIC functionality before tape-out and Software readiness before test-chip came back.• Designed and replaced ASIC technology dependent clocking, memory, and SerDes IPs with FPGA… Show more Technical lead of 3 FPGA engineers to emulate SoC ASIC designs in different phases. Delivered logic and timing accurate FPGA builds to accelerate hardware and software development.• Emulated at least five ASIC chips successfully on time, up to 50M gates size, consisted of high-speed serial links. Ensured ASIC functionality before tape-out and Software readiness before test-chip came back.• Designed and replaced ASIC technology dependent clocking, memory, and SerDes IPs with FPGA counterparts.• Debugging ASIC RTL to make it works for FPGA.• Established and scripted the process-flow for different FPGA platforms to provide consistently truthful prototypes. • Coordinated hardware and software trouble-shooting efforts thru implementing probes and observing the debug builds in the Lab. Show less

Cerritos, Ca

ASIC Verilog HDL design and simulation. Involved PCIX, SATA, 10GBase-X PCS, CAM, and AHB memory controller.

Torrance, Ca

Circuit board and system hardware designer. Defined and designed real-time embedded servo motion controllers. Developed and integrated electro-mechanical robotic system.