-Foundry Engineering-Silicon Failure Analysis Lab

Business Unit leader with overall responsibility for the Client Product Roadmap for notebooks, desktops and workstations across all gaming, consumer and commercial market segments. Driving product definition and attainment to entitlement for performance, power and user experiences including introduction for the first time of AI-powered features run on an AI accelerator integrated into an x86 processor. Revamped long-term roadmap strategy to address evolving market conditions and customer needs.

Global leader delivering foundry technology selection, enablement, ramp and high-volume manufacturing. Responsible for the optimization of foundry technology to maximize performance, yield and reliability for all AMD products. Developed a team of 150 engineers across process technology, design enablement, failure analysis labs and product engineering to maximize the mindshare for AMD at the wafer foundries. Developed technology life cycle process that drove key strategic technology decisions that enabled AMD to make the leap from underdog to market leader.

Overall leader collaborating with AMD’s strategic partner to deliver leading-edge technologies and product ramps to high-volume manufacturing. Grew team from its inception to 20 engineers that were deeply embedded within the foundry process and integration groups. Unblocked production ramps, enabled fast technology transitions, and achieved entitlement performance, yield and reliability across millions of wafers resulting in multiple billions of dollars in revenue.

A key contributor in TI’s migration from internal technology development to joint technology development with the foundries. Led the process technology development to deliver TI’s low power product roadmap. Managed external research programs focused on defining TI’s long-term process technology roadmap.

Responsible for developing gate stack process technology for poly/SiON and high-k/metal gate for the 90nm and 45nm internally developed nodes. This fundamental work resulted in 50 patents, 45 publications, 45 technical presentations and one invited book chapter covering SiON, high-k dielectrics, metal gate electrodes and advanced device structures.