Engineering Manager of a senior security research and engineering team responsible for security research across our entire graphics product road map. Coordinating not only activities within our internal team, but also with external vendors, partnering organizations and researchers both inside and out of Intel. Actively working to strengthen our security stance and hardening our past, present and future products.

Graphics Component Program Manager responsible for the execution of the core team driver development (Kernel Mode Driver/Graphics Memory Management/Power Conservation/General Micro Controller), for both Windows and Linux primarily on Gen11 Graphics (Icelake). Absorbed various Gen10/Gen12/derivative/installer program management duties in addition to Gen11.

Platform Level Program Management of Intel's leading 14nm client product line, supporting the first release of Intel's Core-M processor line in addition to the full stack of Intel's 5th Generation Core processors. Responsible for schedule management, risk management and Change Control Board management requiring close collaboration with manufacturing, architecture, planning, marketing, customer enabling, software, validation, and engineering. Key contributor to our next generation Roll Out Model used as a model for all future Client Computing Group platforms. Launched standard program management solutions on both High End Desktop Platforms as well as Emerging Market Platforms. Drove standardization and reuse across reports and indicators through both SPBI and custom solutions.

Lead PCIe Analog Validation Engineer focused on Pre-Silicon Validation of the Analog Front End for Intel's 6th Generation Core Processors. - Championed validation strategy utilizing both SVTB and Specman verification environments- Owned test plan and validated power saving and performance enhancing features- Mentored team on new validation methodology- Interviewed, hired, and trained incoming employees.DDR Analog Mixed Signal Validation - Managed Cross Site feature implementation, validating fixes, and Memory Controller digital validation on overclocking.

- Sole owner of IvyBridge DDR IO logic design responsible for new power saving features, performance improvements and methodology enhancements.- Developed new RTL and bug fixes for Display, GDXC, and PCIe interfaces- Collaborated with circuit designers to resolve Functional Equivalence Validation issues- Owned Gate Level Simulation flows/debug for all IOs on IvyBridge Lead Silicon

First Rotation: GFX Micro-Architecture FULSIM Gen6GT- Debugged the Command Streamer unit in Advanced Scheduling mode- Improved automation of regression processes to improve agility/reliability of testing and debuggingSecond Rotation: Global Communication Group (Press Relations)- Recreated the Press Room Manager web application used for www.intel.com/Pressroom/- Gained an inside understanding of how PR works at Intel Third Rotation: Folsom Design Center Power Architecture Team- Worked with engineers in Israel on a tool called PETRA used for power modeling- Ran simulations for feasibility analysis of new features during IvyBridge tech readinessREP website core team contributor- Debugged/Enhanced the REP website

Purchase and Manage Rental Properties in the Sacramento Region

Responsible for understanding Sun’s software and presenting to students and staffOrganized location, presentation materials, advertising, and giveaways for all presentations

Supervised the lab to ensure smooth operation, and helped users troubleshoot Unix issues.

- Worked in IPD on Embedded Microprocessors including Intel's first SOC- Lead contact to an outside organization aiding development of a VHDL to Verilog translator- Created cell library data retrieval script, and a Scan Chain analysis script- Evaluated DRC and LVS violations- Received “outstanding” rating on intern review

- Entrepreneurial experience managing marketing, sales, schedule management, recruiting, training, and ultimately production of a small painting business- Rated 100% customer satisfaction on every Job