Doyoung Jang is in the design enabled technology exploration group at imec since 2012. In this role, he is in charge of assessing advanced CMOS technology options using the compact model, TCAD, and hardware data. The Power-Performance-Area (PPA) benchmark has been performed for advanced devices (e.g. FinFET, Nanowire, Nanosheet, III-V, ...) in terms of Design-Technology Co-Optimization (DTCO). He received the Ph.D. degrees in nanoscience and nanotechnology, INP Grenoble, France and in electrical engineering, Korea University, Korea through co-supervising program in 2011.His research experiences began in semiconductor device physics, particularly focused on electrical characterization of low-frequency noise (1/f noise) and device transport in nano-electronic devices such as FinFET, Juntctionless, SiGe nanowire, carbon nanotube, and graphene. In 2012, as a postdoctoral researcher, he joined KIST (Korea Institute of Science and Technology) to study III-V quantum dots and nanowires for single photon sources and also had a teaching experience on quantum mechanics in electronics and laser for graduate students at Korea university.