Janisha Kumar Email & Phone Number

Masters student at Portland State University in Electrical and Computer Engineering. Looking for Entry-Level positions starting from January 2020.My track is SOC/FPGA Verification and Validation. I am also intrested in Computer Architecture.Worked on various project mostly in C++ and System Verilog. Designed a simple DMA using System Verilog and tested it using assertions. Undertaken a project on UPF and performed a brief Static Timing Analysis using TCL Scripting for an ASIC. Other projects are mostly based on Computer Architecture concepts like Cache Line Repalcement and LRU policies. Successfully implemented a Temporal Stream Branch Predictor using Bimodal Branch Predictor as the base predictor. Performed a project to implement MIPS ISA and 5stage pipelining .Apart from this also experienced on working Cadence tool and Python Scripting.