Jason Martzloff Email & Phone Number

Chapel Hill, Nc, Us

Chapel Hill, North Carolina, United States

Raleigh-Durham-Chapel Hill Area

● Direct cutting edge organization providing TCO-friendly solutions in memory, custom physical design, and internal CAD design methodology and tools for first-party artificial intelligence (AI), hardware acceleration, and compute projects● Lead interfaces with other organizational heads and VPs to align on priorities, milestones, impact, and cost of solutions to product● Drive architectural collaborations for AI processor needs in handling sparsity, MACs, massive bandwidth, compute-in-memory, and other optimizations ● Create and present thorough decks for executives on planning, execution, and status● Define all milestones and deliverables for organization and drive alignment with RTL and PD expectations ● Transitioned organization to ADO for efficient and responsible visibility, dependency tracking, and mitigation planning● Installed processes that have led to successfully taping out multiple clean custom IPs including SRAM memories, internally designed register files, and process control monitors on-time in TSMC N3E and N5● Founding member of design team and led recruiting for experts from across industry to ensure a diverse marketplace of ideas

Raleigh-Durham-Chapel Hill Area

Raleigh-Durham-Chapel Hill Area

Raleigh-Durham, North Carolina Area

Was the technical lead, as well as manager, for a team of circuit designers on custom complex register files, datapaths, and arrays throughout Centriq CPU core. I serve as the point person who works with the architects and physical design leads to define new custom macros which alleviate difficult timing, power, or congestion issues. My role includes leading multiple designs, scheduling milestones, deciding work assignments/priorities, and defending technical decisions to high level management.My experience at Qualcomm has been in technology nodes from 65n planar through 7 finFET. I have owned, led and managed several full-custom register files, CAMs and multi-port macro designs. Additionally, I have owned and led SRAM-based designs using foundry LR(8T) and HC(6T) DRC-waivered bit cells which include multiple power domains. The design process started with feasibility work and architecting continuing through design and hardware characterization.In addition to hardware work, I have authored software tools that allow the design team to be more efficient. Most of this work has been done in Ruby, before that I used Perl. I created the interface tool that the entire design team continues to use for physical, DRC/LVS, verification and extraction as well as a tool that allows the entire circuit design team efficiently run RTL-to-schematic equivalence in Synopsys ESP much more expeditiously.More recently I have been working on tools to provide designers more information based on all of the data they collect across corners. This has allowed users to visually and graphically inspect the effects of PVT across timing margins leading to quicker closure.

Raleigh-Durham, North Carolina Area

Lead circuit designer on team that delivers numerous CAMs, dual-rail SRAM arrays and dual- and multi-port register file transistor level designs for Snapdragon products with work from 90 nm planar to current 7 nm finfet.

Raleigh-Durham, North Carolina Area

Burlington, Ma

Designed synthesized logic blocks and a full custom single-cycle CAM-RAM structure at transistor level from feasibility through final tapeout. Also awarded the Sun Falcon Award for testing of and improvements to the in-house synthesis flow.

Shrewsbury, Massachusetts, United States

It was a co-op but it was on Alpha EV7 and Araña designing LFSRs in Tbox. The brilliant people that I got to learn from, and with, ignited my love for processor design.