Jason Mcneely Email and Phone Number

•Collaborated with multiple cross functional teams to developed key experience indicators used to evaluate performance, responsiveness, and power efficiency ensuring Devices meet EVO certification. • Conducted competitive analysis of AMD and Apple systems, providing critical insights for future product definition. • Collaborated with architecture team to deliver power and performance data for future product projections.

• Post-silicon SOC Power and Performance Validation Directly responsible for power and performance validation of post silicon system on chip from initial power on to product release. Validation of dynamic capacitance, leakage, and total dissipated power. Performance validation and tuning with specialization in Fabric Intel Speed Step technology enabling and tuning Found engineering milestone gating bandwidth counter hardware bug and validated… Show more • Post-silicon SOC Power and Performance Validation Directly responsible for power and performance validation of post silicon system on chip from initial power on to product release. Validation of dynamic capacitance, leakage, and total dissipated power. Performance validation and tuning with specialization in Fabric Intel Speed Step technology enabling and tuning Found engineering milestone gating bandwidth counter hardware bug and validated solution Root caused and provided the solution for critical Speed Step performance bug on 12th Gen SOC Memory bandwidth and latency validation and tuning Found local control microcode bug and validated solution Platform power management power delta validation and tuning Worked with pcode team and power architecture team to develop and tune power reporting algorithm • Custom tool development Designed and developed custom tools and automation to streamline validation and tuning of 12th generation SOC features. Hardware verification tool: requested hardware configuration information from the system under test and cross referenced with a database to verify the hardware was correctly configured for the specific test suite being run. Wrote software used to post process data collected. Capable of extracting and aggregating specific data for presentation to project leads. • Test plan development Owned post-silicon power and performance validation of memory subsystem for intel 13th generation processor family collaborating closely with cross functional teams. Worked with architecture, performance, and power architecture teams to develop the validation plan and dependencies to ensure functional, power, and performance targets were met. Show less