Responsible for the following project design from hardware architecture design to deliver the product:- 32G PCIe/NVME/CXL Protocol Exerciser and Analyzer- 400G Ethernet/64G FC Protocol Analyzer.

Managed the Hardware Department to develop 16G PCIe/NVME, 200G Ethernet/32G FC, SAS/SATA, USB, DDR Protocol Analyzer, established hardware team Schematic, PCB, Board and system test roles.

As a senior Staff engineer, successfully designed the following products:• PCIe G4/3 Protocol Exerciser and Analyzer and Related products• 8G/16G FC and 10G/40G Ethernet Protocol Analyzer.• SAS/SATA 12G Protocol Analyzer• DDR3/4 Protocol Analyzer and Related products

As a Sr. Design Manager, led the hardware team to handle all road-map production and customer ODM production design, the following important roles were played:• Created Architectural Design Specification for each production design.• Defined the hardware design rules to make sure all design phases can be done efficiently and correctly.• Designed the complicated Enterprise SATA III SSD which supported ONFI 2.0 and Toggle Mode NAND flash accessing.• Managed all Unigen road-map and customer ODM production design, and released it to mass production successfully. It coved SATA/SAS SSD, ODM SSD, DDR2/DDR3 module, WiFi and Bluetooth module, USB flash, SD/CF flash cards design.• Led the team to analyze RMA failure and gave the solution to fix.

As a principal design consultant, I had worked for PCI Express G3/2 products in the following roles:As a design engineer, designed PCI Express Gen3/2 Exerciser. PCIe G3/2 Exerciser is next generation PCIe trainer, which can generate all kind of PCIe patterns and monitor PCIe traffic from customer designed product at up to 8GBPS speed. This system is design on standard PCIe half size card, and has the CPU system and complicated FPGA on it. I started design this system from concept and finished it as a successful product by end of March 2010. In this project, the following roles were played:Concept Design.Schematic Design.Signal integrity and PCB layout supervise.System/Board bring-up and test procedure Design.Product support.As a team leader, worked on PCI Express Gen 3/2 Analyzer.PCIe G3/2 Analyzer is next generation PCIe production in LeCroy, which can monitor/recording/analysis PCIe traffic from customer designed product at up to 8GBPS speed. This is a complicate system that includes Controller, Recorder and Analyzer sub-system. In this project, the following roles were played:Test Automation System Architecture Design.System Test Procedure Design. Leading the team members to Bring-up/Troubleshoot the system.Working with the FAB house and production group to analyze the fail system.

As a leading engineer, I had worked for the different projects and have made the great contribution to the following tasks:SD IF Playback System Design. This is ARM microcontroller based system which is implemented in Xilinx Virtex FPGA, it continuously captures or playback high speed GPS IF data stream to/from high speed SDHC card through DMA mode, it is designed for validating GPS chip performance.In this project, the following roles were played:System Architecture Design.FPGA Logic Design and Implementation, which includes ARM and SDIO IP integration, RTL coding and simulation, FPGA Synthesis and place & Route, Timing Analysis.Technical lead for this design group.Pre-Silicon and Post-Silicon Validation Hardware Design for GPS Receiver Chip.I had worked the following fields: New Post-Silicon platform architecture design.Pre-Silicon Validation Platform required functional boards design; it includes Communication Interface Board, Memory Board, RF Interface Board and others.Post-Silicon Validation Platform required interface boards design.FPGA logic design for post-silicon GPS receiver chips validation.Signal Integrity on SOC Evaluation and reference board.I had completed the signal integrity on mDDR/DDR2 interface design for SOC chip on Evaluation and Tier 1 customer design boards, led the SOC hardware team to fix the design problem quickly and got the solid performances on Tier 1 customer's GPS products.

As a leading engineer, I had worked for the followoing different projects as the Architecture designer, Hardware designer, FPGA logic designer, and Signal Integrity engineer:- Charger CDG Systerm.- X Timing Controller board (XTC).- Charger Interface Board- CDG Stage Interface Board- High Speed Driver Board.- Acquisition Controller Board.- High/low Current Source Board- AZP board.On thw above projects, x86 CPU, PowerPC, DSP, DDR, Fiber Channel, Gigabit Ethernet, PCI/cPCI/VME, I2C/SPI technology involved to the design.

As a key engineer, designed Digital Receive and Processing Board for Radio Camera System, which was used in the E911 cellphone caller locating application for AMPS, DAMPS, CDMA and GSM standard.

As a Key engineer, designed hardware and FPGA logic on Digital IF Receiver and Baseband Processing Boards, which are used for Soft Radio Base Station - WCDMA project.