• Initiated a new research project in fault-tolerant microprocessor design.• Secured research funding for three graduate students through writing grant proposals and collaborative work with industry members.• Coordinated a team of two junior graduate students, directing them in research and development.• Designed and implemented a framework for conducting statistical timing analysis of circuit simulations for an embedded microprocessor core.• Implemented an ARM instruction set code generator for the Trimaran Research Compiler (www.trimaran.org)

• Constructed a generic framework for analyzing the circuit-level effects of transient faults within ARM microprocessors.• Devised a statistical technique for the protection of logic against transient faults.• Invented a novel cache structure for protecting register files from transient faults.• Filed three patent applications based on the results of the above work.