Jasper Bai Email & Phone Number

San Jose, California, United States

System-level architecture design: Responsible for defining and designing the system-level architecture of ASIC, including complex processing units, memory subsystems and interfacesProject planning: Participate in the requirements analysis, planning and definition of the project, and develop detailed design plans and schedules.Technological innovation: Promote technological innovation, explore new technologies and methods, and enhance design capabilities and competitive advantages.

San Jose, California, United States

responsible for developing and designing high-level technical architecture to ensure that the overall design of the system meets performance, power consumption and functional requirements.making key technical decisions and selecting appropriate tools, methods and technical solutions.

Santa Clara, California, United States

Project Planning: Develop project plans and schedules, including resource allocation, milestone setting, and budget management.Project Management: Responsible for leading and managing ASIC design projects, coordinating the work of team members, and ensuring that projects are completed on time.Technical Guidance: Provide technical guidance and support to team members to solve complex problems encountered during the design process.

Santa Clara, California, United States

System-level architecture: Design and define the system-level architecture of the ASIC, including complex functional modules and interfaces.High-level RTL design: Use high-level hardware description languages (such as Verilog or VHDL) for complex circuit design and functional modeling.Performance optimization: Perform design optimization to ensure that the chip achieves the best results in terms of performance, power consumption and area.

Santa Clara, California, United States

Front-end design: includes RTL (Register Transfer Level) design, hardware description language (such as Verilog or VHDL) programming, functional modeling and simulation.Logic design: Develop and verify the logic circuit of ASIC to ensure that the design meets the expected functions and performance standards.

San Jose, California, United States

Responsible for the physical layout design of integrated circuits, ensuring that the circuit layout on the chip is optimized.