Jasper Chen Email & Phone Number

BT Sleep Power●Reduce BT sleep power by powering down digital and analogue blocks as much as possible.●Separate SRAM retention control and power switch control, giving the FW the flexibility to consider wakeup latency and power savings.●Improving power efficiency through proper use of BUCKs and LDOs.●Consider design to control sleep/wake sequence, such as isolation, retention, PSWs, etc.●Implementing power-aware design through UPF, including UPF simulation, synthesis and VCLP check.●Power analysis using PrimePower and Spyglass Power.

台灣 Taipei City 台北

Taipei City, Taiwan

I2S/TDM, PDM ControllerSoundWire SlaveNVMe ControllereMMC Device Controller - Already got eMMC AVL approval from Hisilicon & Allwinner & Rockchip & Amlogic & Actions, and project database is qualified by US companiesSD/SDIO Host/Device ControllerLegecy/ONFI/Toggle NAND Flash ControllerDDR/DDR2/LPDDR2 SDRAM ControllerUSB2.0/3.0 DeviceI2C, SPI, UARTSOC IC DesignIC Front-End Design RTL Coding, UVM Verification Spyglass CDC DCG Synthesis, DC Scan-Chain Insertion, TMAX ATPGXilinx FPGA emulationLow Power Design (UPF)

Taipei City, Taiwan

Disk RAID ControllerFPGA Implementation and mass production

Taipei City, Taiwan

Ethernet SwitchLogic Design & Verification

Master'S Degree, Electrical Engineering, Communication

Bachelor'S Degree, Computer And Communication Engineering