Jatinder Singh Email & Phone Number

Bangalore, India

Reaching out to research institutes / organizations for their requirements for subsystem development, IC backend design as well as board designs. Responsible for capturing the customer requirements and ensure Customer Agreement/ Proposal is reviewed by appropriate and cognizant functional areas. Coordination with all external Agencies whose assistance is required to meet customers’ requirements. Review and approve Customer Agreements and proposals and also negotiate price. Ensures customer communication channels and interfaces are established, as appropriate and respond to customer inquiries. Responsible for timely delivery of products and services

Responsible for capturing the customer requirements. Interface with Foundry or IP provider to meet customer requirements. Evaluate the customer requirements and setup the design team, EDA design tools and compute infrastructure. Engage with all external agencies for resource augmentation any other assistance required to meet customers’ requirements. Evaluate startup in India for possible use of IP and Design Services for executing the projectsASIC Design activity Implemented EDA design flow on Synopsys EDA tools and developed rule decks for StarRC parasitic extraction. Developed and implemented rule decks for Calibre DRC, LVS & PEX parasitic extraction. Back-end design of ASICs, Interface with the Foundry to realize the designs, Qualify realized design using PCM test data and ASIC test data. Involved in MEMS Sensors ROIC designs. Full chip Physical Verification of ASICs and ROICs. Interface with Assembly, Packaging & TestingPDK Development & migration to Open Access Developed PDK for 1 micron CMOS Process using Cadence PDK Development Tools PDK Auto System (PAS) and System for Testing PDKs (STeP). Successfully migrated Standard & IO Cells from Cadence DWII (4.1.x) to OA database. Migrated rule decks from Diva to Assura DRC, LVS & QRC parasitic extraction

Uncooled Micro-bolometer developmentInvolved on development of Titanium based 64x64 microbolometer array. Completed Mask Set design and involved Process flow for fabrication. Involved in Process Integration of microbolometer array and coordinated the fabrication activity.MEMS device development and fabrication initiativeDemonstrated Surface Micromachining in existing CMOS Foundry which opened a new opportunity for SITAR. Designed basic MEMS devices and created an Engineering Mask Set for MEMS process development activity. Successfully developed and demonstrated MEMS fabrication process Discrete devices development Completed the task of exploring fabrication of Discrete & MEMS devices is existing CMOS fabrication facility. Mask Set design and fabrication of discrete devices such as Depletion mode MOSFET, Radiation Dosimeter, Photo Diode Array, Dual Dielectric MOSFET, Silicon Photo Multiplier, Silicon Tips etc. Evolved Process flow for fabrication of various devices and developed Unit processes and run short loops. Created of Run-card (Fabrication Process Sequence) for Foundry. Involved in development of Process Control Monitors for qualifying the proces

Mask Data PreparationResponsible for frame generation and optimization the placement of process and mask specific items into the scribe lines for both regular arrays of dies and Multi-Project Wafers (MPWs). Subsequently generate final mask layouts according to user-defined templates, supporting scaling of mask, Multi-Layer and Multi Field Masks. Verification of mask set database to ensure that the data error free and can be manufactured.Software / Database Application development Assigned the development of Database application for Fab Automation based on Oracle database software. Involved in development of “Lot Traveler” application for automated ASIC Fabrication process flow and record of Process Recipes and Process Parameters. Involved in development of “Fab Equipment Maintenance” application for scheduling Preventive Maintenance, record of Breakdown Maintenance and Spares Inventory