Jawad Nasrullah Email & Phone Number

Palo Alto, California, US

Heterogeneous integrated circuits and systems product R&D for clients. Helping enable semiconductor 3D-ICs with Chiplets for efficient and performance computing.

Thermal, power, and cooling systems solutions for chiplets, advanced semiconductor packaging, and electronics products.

Pushing industry-wide standardization of open and interoperable chiplet-based architectures for performance computing. (https://www.opencompute.org/wiki/Server/ODSA)

Collaborative consortium for chiplet-based design and manufacturing in the semiconductor industry.

Mountain View, CA

Semiconductor Chiplet Startup that helped bring silicon back to the Silicon Valley. And it all started at StartX.Stanford.Edu.

Suwon-Si, Gyeonggi-Do, KR

Developed low-power and power integrity enhancement design technologies for use in mobile and server SoCs.

Santa Clara, California, US

• Developed low-power silicon architecture and circuit solutions for 22/14/10nm microprocessors—several patent pending inventions:
• Led a team of six through tech readiness for a multi GHz synthesizable design. Micro-architected key critical paths, simplified logic and re-partitioned the design to reduce custom designed components. Demonstrated.
• Developed OOK based leakage management scheme to achieve effective sub-Vmin speed and lowered power while maintaining electrical Vmin and corresponding speed.
• Estimated die area and power dissipation by estimating and combining area and energy costs of individual components with activity factors.
• Developed a dual Vcc RF design for state retention during sleep mode, while reducing leakage.
• Developed a Vmin reduction scheme based on adaptive cache line disabling method.

Palo Alto, CA, US

• Design lead for a high-speed SerDes/IO design team. Designed 12/16Gbps SerDes IOs:
• Developed 3rd generation 16-core chip multi-threading microprocessor (Rock CPU). Contributed to multi GHz IO/SerDes design, power estimation, and device technology characterization.
• Member of Rock CPU power task force: estimated, budgeted, and designed for power reduction.
• Hands-on circuit design of equalizers, input buffers, termination, offset cancellation. Synthesized digital control and datapath blocks. Performed PLL jitter analysis. Handled top-level of IO testchips.
• Technical lead for foundry interface on 40nm and 28nm mixed-signal/analog device technology.
• Designed L2 ECC related blocks using APR, STA, and SoC backend flows for SPARC-T3 processor.

US

• Developed body-bias based leakage management (LongRun2) technology for low power designs:
• Designed LongRun2 device technology validation platform (65nm, 45nm) for several customers.
• Hands on design porting of voltage regulators, bias generators, and sensors for power management.
• Developed device designs for back-bias performance improvement.
• Researched ESD schemes for body-biased ICs. Performed lab testing and bring-up of various chips.
• Technology Licensees: NEC, Sony, Fujitsu, Toshiba.

• Designed USB2.0 SerDes/transceiver analog front end:
• Hands on design of squelch detector, receiver, driver, over-voltage protection, and termination auto calibration circuitry.
• Project lead and manager for a team of 5 for the design integration and delivery of several production-ready macros and testchips.
• Supported USB phy debug and bring up on early version of iPod. Debugged a major signaling problem due to excessive capacitance and provided an on board inductor solution that helped ship the product.
• Technology Licensees: LSI Logic, National, Motorola, PortalPlayer.

Stanford, CA, US

Technology development for ultra-low-power design.

San Jose, CA, US

High Precision Analog to Digital Converter (ADC) bench testing.

ADSL modem noise source modeling and testing.

Telecom consultancy

Electromedical equipment support.

Phd, Electrical Engineering

Ms, Electrical Engineering

B.Sc. With Honors, Electrical Engineering